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| author | Suman Anna <s-anna@ti.com> | 2019-12-02 16:34:21 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-12-09 14:00:24 -0500 |
| commit | 1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7 (patch) | |
| tree | 450ae9084e1421449b32fa40fc8669858ef59f41 /board/raspberrypi | |
| parent | ac1ca99926606faf5e2d37771680ed97d66ee5ab (diff) | |
| download | u-boot-1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7.zip u-boot-1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7.tar.gz u-boot-1045ff4d1af9e3e8a2ad4cf04a7263d49e90cfa7.tar.bz2 | |
ARM: DRA7: Fixup DSP OPP_HIGH clock rate on DRA76P/DRA77P SoCs
The commit 1b42ab3eda8a ("ARM: DRA7: Fixup DSPEVE, IVA and GPU clock
frequencies based on OPP") added the core logic to update the kernel
device-tree blob to adjust the DSP, IVA and GPU DPLL clocks based on
a one-time OPP choice selected in U-Boot for most of the DRA7xx/AM57xx
family of SoCs.
The DSPs on DRA76xP/DRA77xP SoCs (DRA76x ACD package SoCs) though
provide a higher performance and can run at a higher clock frequency
of 850 MHz at OPP_HIGH instead of 750 MHz. Fix up the logic to use the
correct clock rates on these SoCs. Note that this higher clock rate is
not applicable to other Jacinto 6 Plus SoCs (DRA75xP/DRA74xP SoCs or
AM574x SoCs) that follow the ABZ package.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'board/raspberrypi')
0 files changed, 0 insertions, 0 deletions