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| author | Teresa Remmet <t.remmet@phytec.de> | 2021-07-07 12:58:01 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-07-10 16:53:34 +0200 |
| commit | 0f166b85ac473f72aaff6489f880d26cc41a1148 (patch) | |
| tree | 25e5d900d1e578235bf076d11d97dc6364fa2cc1 /board/phytec | |
| parent | 60f64bec414e139baa8764b56071eb22a1460c36 (diff) | |
| download | u-boot-0f166b85ac473f72aaff6489f880d26cc41a1148.zip u-boot-0f166b85ac473f72aaff6489f880d26cc41a1148.tar.gz u-boot-0f166b85ac473f72aaff6489f880d26cc41a1148.tar.bz2 | |
board: phytec: phycore_imx8mp: Set VDD_ARM to 0,95V
Increase VDD_ARM to prevent timing issues as VDD_SOC is
used in OD mode. Also increase GIC clock.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Diffstat (limited to 'board/phytec')
| -rw-r--r-- | board/phytec/phycore_imx8mp/spl.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index 0bc4c76..815ca9b 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -62,7 +62,8 @@ int power_init_board(void) /* BUCKxOUT_DVS0/1 control BUCK123 output */ pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); - /* increase VDD_SOC to typical value 0.95V */ + /* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C); /* set WDOG_B_CFG to cold reset */ @@ -71,6 +72,14 @@ int power_init_board(void) return 0; } +void spl_board_init(void) +{ + /* Set GIC clock to 500Mhz for OD VDD_SOC. */ + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +} + int board_fit_config_name_match(const char *name) { return 0; |