diff options
author | wdenk <wdenk> | 2004-03-25 19:29:38 +0000 |
---|---|---|
committer | wdenk <wdenk> | 2004-03-25 19:29:38 +0000 |
commit | 0608e04da9d0df5d00cf48a1d9141e2ea1bc9635 (patch) | |
tree | 28fa0ea5f1d70d9bae2eaca42643804235141d12 /board/kup/kup4k | |
parent | b79a11cc2bda7a4d5e00444427a0d06b4e86a990 (diff) | |
download | u-boot-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.zip u-boot-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.tar.gz u-boot-0608e04da9d0df5d00cf48a1d9141e2ea1bc9635.tar.bz2 |
* Patch by Klaus Heydeck, 13 Mar 2003:
Add support for KUP4X Board
Diffstat (limited to 'board/kup/kup4k')
-rw-r--r-- | board/kup/kup4k/Makefile | 40 | ||||
-rw-r--r-- | board/kup/kup4k/config.mk | 28 | ||||
-rw-r--r-- | board/kup/kup4k/kup4k.c | 458 | ||||
-rw-r--r-- | board/kup/kup4k/s1d13706.h | 174 | ||||
-rw-r--r-- | board/kup/kup4k/u-boot.lds | 141 | ||||
-rw-r--r-- | board/kup/kup4k/u-boot.lds.debug | 135 |
6 files changed, 976 insertions, 0 deletions
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile new file mode 100644 index 0000000..5732044 --- /dev/null +++ b/board/kup/kup4k/Makefile @@ -0,0 +1,40 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o ../common/flash.o ../common/kup.o + +$(LIB): .depend $(OBJS) + $(AR) crv $@ $(OBJS) + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/kup/kup4k/config.mk b/board/kup/kup4k/config.mk new file mode 100644 index 0000000..22e30b2 --- /dev/null +++ b/board/kup/kup4k/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# KUP4K board +# + +TEXT_BASE = 0x40000000 diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c new file mode 100644 index 0000000..8bed3d5 --- /dev/null +++ b/board/kup/kup4k/kup4k.c @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8xx.h> +#include "../common/kup.h" +#ifdef CONFIG_KUP4K_LOGO + #include "s1d13706.h" +#endif + +#undef DEBUG +#ifdef DEBUG +# define debugk(fmt,args...) printf(fmt ,##args) +#else +# define debugk(fmt,args...) +#endif + +typedef struct { + volatile unsigned char *VmemAddr; + volatile unsigned char *RegAddr; +} FB_INFO_S1D13xxx; + + +/* ------------------------------------------------------------------------- */ + +#if 0 +static long int dram_size (long int, long int *, long int); +#endif + +#ifdef CONFIG_KUP4K_LOGO +void lcd_logo(bd_t *bd); +#endif + + +/* ------------------------------------------------------------------------- */ + +#define _NOT_USED_ 0xFFFFFFFF + +const uint sdram_table[] = { + /* + * Single Read. (Offset 0 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, + 0x1FF77C47, /* last */ + + /* + * SDRAM Initialization (offset 5 in UPMA RAM) + * + * This is no UPM entry point. The following definition uses + * the remaining space to establish an initialization + * sequence, which is executed by a RUN command. + * + */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + + /* + * Burst Read. (Offset 8 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Single Write. (Offset 18 in UPMA RAM) + */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Burst Write. (Offset 20 in UPMA RAM) + */ + 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Refresh (Offset 30 in UPMA RAM) + */ + 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, + + /* + * Exception. (Offset 3c in UPMA RAM) + */ + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, +}; + +/* ------------------------------------------------------------------------- */ + + +/* + * Check Board Identity: + */ + +int checkboard (void) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + uchar *latch,rev,mod; + + /* + * Init ChipSelect #4 (CAN + HW-Latch) + */ + immap->im_memctl.memc_or4 = 0xFFFF8926; + immap->im_memctl.memc_br4 = 0x90000401; + + latch=(uchar *)0x90000200; + rev = (*latch & 0xF8) >> 3; + mod=(*latch & 0x03); + printf ("Board: KUP4K Rev %d.%d SN: %s\n",rev,mod,getenv("ethaddr")); + return (0); +} + +/* ------------------------------------------------------------------------- */ + +long int initdram (int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + long int size_b0 = 0; + long int size_b1 = 0; + long int size_b2 = 0; + + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + + /* + * Preliminary prescaler for refresh (depends on number of + * banks): This value is selected for four cycles every 62.4 us + * with two SDRAM banks or four cycles every 31.2 us with one + * bank. It will be adjusted after memory sizing. + */ + memctl->memc_mptpr = CFG_MPTPR; + + memctl->memc_mar = 0x00000088; + + /* + * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at + * preliminary addresses - these have to be modified after the + * SDRAM size has been determined. + */ +/* memctl->memc_or1 = CFG_OR1_PRELIM; */ +/* memctl->memc_br1 = CFG_BR1_PRELIM; */ + +/* memctl->memc_or2 = CFG_OR2_PRELIM; */ +/* memctl->memc_br2 = CFG_BR2_PRELIM; */ + + + memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + + udelay (200); + + /* perform SDRAM initializsation sequence */ + + memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + udelay (1); + memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + udelay (1); + memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + udelay (1); + memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + udelay (1); + memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + udelay (1); + + memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + udelay (1000); + +#if 0 /* 3 x 8MB */ + size_b0 = 0x00800000; + size_b1 = 0x00800000; + size_b2 = 0x00800000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF800A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFF000A00; + memctl->memc_br2 = 0x00800081; + memctl->memc_or3 = 0xFE000A00; + memctl->memc_br3 = 0x01000081; +#else /* 3 x 16 MB */ + size_b0 = 0x01000000; + size_b1 = 0x01000000; + size_b2 = 0x01000000; + memctl->memc_mptpr = CFG_MPTPR; + udelay (1000); + memctl->memc_or1 = 0xFF000A00; + memctl->memc_br1 = 0x00000081; + memctl->memc_or2 = 0xFE000A00; + memctl->memc_br2 = 0x01000081; + memctl->memc_or3 = 0xFC000A00; + memctl->memc_br3 = 0x02000081; +#endif + + udelay (10000); + + return (size_b0 + size_b1 + size_b2); +} + +/* ------------------------------------------------------------------------- */ + +/* + * Check memory range for valid RAM. A simple memory test determines + * the actually available RAM size between addresses `base' and + * `base + maxsize'. Some (not all) hardware errors are detected: + * - short between address lines + * - short between data lines + */ +#if 0 +static long int dram_size (long int mamr_value, long int *base, + long int maxsize) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl = &immap->im_memctl; + volatile long int *addr; + ulong cnt, val; + ulong save[32]; /* to make test non-destructive */ + unsigned char i = 0; + + memctl->memc_mamr = mamr_value; + + for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { + addr = base + cnt; /* pointer arith! */ + + save[i++] = *addr; + *addr = ~cnt; + } + + /* write 0 to base address */ + addr = base; + save[i] = *addr; + *addr = 0; + + /* check at base address */ + if ((val = *addr) != 0) { + *addr = save[i]; + return (0); + } + + for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { + addr = base + cnt; /* pointer arith! */ + + val = *addr; + *addr = save[--i]; + + if (val != (~cnt)) { + return (cnt * sizeof (long)); + } + } + return (maxsize); +} +#endif + +int misc_init_r (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_STATUS_LED + volatile immap_t *immap = (immap_t *) CFG_IMMR; +#endif +#ifdef CONFIG_KUP4K_LOGO + bd_t *bd = gd->bd; + + lcd_logo (bd); +#endif /* CONFIG_KUP4K_LOGO */ +#ifdef CONFIG_IDE_LED + /* Configure PA8 as output port */ + immap->im_ioport.iop_padir |= 0x80; + immap->im_ioport.iop_paodr |= 0x80; + immap->im_ioport.iop_papar &= ~0x80; + immap->im_ioport.iop_padat |= 0x80; /* turn it off */ +#endif + setenv("hw","4k"); + poweron_key(); + return (0); +} + +#ifdef CONFIG_KUP4K_LOGO + + +void lcd_logo (bd_t * bd) +{ + FB_INFO_S1D13xxx fb_info; + S1D_INDEX s1dReg; + S1D_VALUE s1dValue; + volatile immap_t *immr = (immap_t *) CFG_IMMR; + volatile memctl8xx_t *memctl; + ushort i; + uchar *fb; + int rs, gs, bs; + int r = 8, g = 8, b = 4; + int r1, g1, b1; + int n; + uchar tmp[64]; /* long enough for environment variables */ + int tft = 0; + + immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); + immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ + immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); + +/*----------------------------------------------------------------------------- */ +/* Initialize the chip and the frame buffer driver. */ +/*----------------------------------------------------------------------------- */ + memctl = &immr->im_memctl; + + + /* + * Init ChipSelect #5 (S1D13768) + */ + memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ + memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ + + fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); + fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); + + if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) + || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { + printf ("Warning:LCD Controller S1D13706 not found\n"); + setenv ("lcd", "none"); + return; + } + + + for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { + s1dReg = aS1DRegs_prelimn[i].Index; + s1dValue = aS1DRegs_prelimn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = + s1dValue; + } + + + n = getenv_r ("lcd", tmp, sizeof (tmp)); + if (n > 0) { + if (!strcmp ("tft", tmp)) + tft = 1; + else + tft = 0; + } +#if 0 + if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) + tft = 0; + else + tft = 1; +#endif + + debugk ("Port=0x%02x -> TFT=%d\n", tft, + ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); + + /* init controller */ + if (!tft) { + for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { + s1dReg = aS1DRegs_stn[i].Index; + s1dValue = aS1DRegs_stn[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_stn[i].Index, + aS1DRegs_stn[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = + s1dValue; + } + n = getenv_r ("contrast", tmp, sizeof (tmp)); + ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = + (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; + switch (bd->bi_busfreq) { + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; + break; + case 48000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; + break; + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 64000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; + break; + } + /* setenv("lcd","stn"); */ + } else { + for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { + s1dReg = aS1DRegs_tft[i].Index; + s1dValue = aS1DRegs_tft[i].Value; + debugk ("s13768 reg: %02x value: %02x\n", + aS1DRegs_tft[i].Index, + aS1DRegs_tft[i].Value); + ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = + s1dValue; + } + + switch (bd->bi_busfreq) { + default: + printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); + case 40000000: + ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; + ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; + break; + } + /* setenv("lcd","tft"); */ + } + + /* create and set colormap */ + rs = 256 / (r - 1); + gs = 256 / (g - 1); + bs = 256 / (b - 1); + for (i = 0; i < 256; i++) { + r1 = (rs * ((i / (g * b)) % r)) * 255; + g1 = (gs * ((i / b) % g)) * 255; + b1 = (bs * ((i) % b)) * 255; + debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); + S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), + (b1 >> 4)); + } + + /* copy bitmap */ + fb = (char *) (fb_info.VmemAddr); + memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); +} +#endif /* CONFIG_KUP4K_LOGO */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h new file mode 100644 index 0000000..cd5eccc --- /dev/null +++ b/board/kup/kup4k/s1d13706.h @@ -0,0 +1,174 @@ +/*---------------------------------------------------------------------------- */ +/* */ +/* File generated by S1D13706CFG.EXE */ +/* */ +/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ +/* All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------- */ + +/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ + +#define S1D_DISPLAY_WIDTH 320 +#define S1D_DISPLAY_HEIGHT 240 +#define S1D_DISPLAY_BPP 8 +#define S1D_DISPLAY_SCANLINE_BYTES 320 +#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L +#define S1D_PHYSICAL_VMEM_SIZE 0x14000L +#define S1D_PHYSICAL_REG_ADDR 0x80080000L +#define S1D_PHYSICAL_REG_SIZE 0x100 +#define S1D_DISPLAY_PCLK 6250 +#define S1D_PALETTE_SIZE 256 +#define S1D_REGDELAYOFF 0xFFFE +#define S1D_REGDELAYON 0xFFFF + +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ + ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ + ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ + ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ +} + +#define S1D_READ_PALETTE(p,i,r,g,b) \ +{ \ + ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ + r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ + g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ + b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ +} + +typedef unsigned short S1D_INDEX; +typedef unsigned char S1D_VALUE; + + +typedef struct +{ + S1D_INDEX Index; + S1D_VALUE Value; +} S1D_REGS; + + +static S1D_REGS aS1DRegs_prelimn[] = +{ + {0x10,0x00}, /* PANEL Type Register */ + {0xA8,0x00}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + +}; + +static S1D_REGS aS1DRegs_stn[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x10,0xD0}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xF0}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x80}, /* Vertical Sync Pulse Width Register */ + {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x83}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; + +static S1D_REGS aS1DRegs_tft[] = +{ + {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ + {0x05,0x42}, /* PCLK Config Register */ + {0x10,0x61}, /* PANEL Type Register */ + {0x11,0x00}, /* MOD Rate Register */ + {0x12,0x30}, /* Horizontal Total Register */ + {0x14,0x27}, /* Horizontal Display Period Register */ + {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ + {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ + {0x18,0xFA}, /* Vertical Total Register 0 */ + {0x19,0x00}, /* Vertical Total Register 1 */ + {0x1C,0xEF}, /* Vertical Display Period Register 0 */ + {0x1D,0x00}, /* Vertical Display Period Register 1 */ + {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ + {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ + {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ + {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ + {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ + {0x24,0x00}, /* Vertical Sync Pulse Width Register */ + {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ + {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ + {0x70,0x03}, /* Display Mode Register */ + {0x71,0x00}, /* Special Effects Register */ + {0x74,0x00}, /* Main Window Display Start Address Register 0 */ + {0x75,0x00}, /* Main Window Display Start Address Register 1 */ + {0x76,0x00}, /* Main Window Display Start Address Register 2 */ + {0x78,0x50}, /* Main Window Address Offset Register 0 */ + {0x79,0x00}, /* Main Window Address Offset Register 1 */ + {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ + {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ + {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ + {0x80,0x50}, /* Sub Window Address Offset Register 0 */ + {0x81,0x00}, /* Sub Window Address Offset Register 1 */ + {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ + {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ + {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ + {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ + {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ + {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ + {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ + {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ + {0xA0,0x00}, /* Power Save Config Register */ + {0xA1,0x00}, /* CPU Access Control Register */ + {0xA2,0x00}, /* Software Reset Register */ + {0xA3,0x00}, /* BIG Endian Support Register */ + {0xA4,0x00}, /* Scratch Pad Register 0 */ + {0xA5,0x00}, /* Scratch Pad Register 1 */ + {0xA8,0x01}, /* GPIO Config Register 0 */ + {0xA9,0x80}, /* GPIO Config Register 1 */ + {0xAC,0x01}, /* GPIO Status Control Register 0 */ + {0xAD,0x00}, /* GPIO Status Control Register 1 */ + {0xB0,0x10}, /* PWM CV Clock Control Register */ + {0xB1,0x80}, /* PWM CV Clock Config Register */ + {0xB2,0x00}, /* CV Clock Burst Length Register */ + {0xAD,0x80}, /* reset seq */ + {0x70,0x03}, +}; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds new file mode 100644 index 0000000..2339136 --- /dev/null +++ b/board/kup/kup4k/u-boot.lds @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) +/* + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_ppc/ppcstring.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + lib_generic/zlib.o (.text) + + . = env_offset; + common/environment.o(.text) +*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug new file mode 100644 index 0000000..4e369d5 --- /dev/null +++ b/board/kup/kup4k/u-boot.lds.debug @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/mpc8xx/start.o (.text) + common/dlmalloc.o (.text) + lib_generic/vsprintf.o (.text) + lib_generic/crc32.o (.text) + + . = env_offset; + common/environment.o(.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} |