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| author | Tim Harvey <tharvey@gateworks.com> | 2022-03-30 13:39:02 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-03-31 08:27:52 -0400 |
| commit | 52ae8d6cc8b2f4ec53228e1d9216b5d9071cb325 (patch) | |
| tree | 37fd38e4ec59c6abcf1cc9c23c5bef1c09393dd4 /board/gateworks | |
| parent | ce1cbf1ae0be6c13fb32e7abc8fa358bb5244bf5 (diff) | |
| download | u-boot-52ae8d6cc8b2f4ec53228e1d9216b5d9071cb325.zip u-boot-52ae8d6cc8b2f4ec53228e1d9216b5d9071cb325.tar.gz u-boot-52ae8d6cc8b2f4ec53228e1d9216b5d9071cb325.tar.bz2 | |
board: gateworks: venice: determine dram size at runtime
The SPL does not update the memory node with the dram size from EEPROM
but instead we can use get_ram_size which does a simple memory test
to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that
is the max used on the Venice boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Diffstat (limited to 'board/gateworks')
| -rw-r--r-- | board/gateworks/venice/venice.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c index 4e05802..5334500 100644 --- a/board/gateworks/venice/venice.c +++ b/board/gateworks/venice/venice.c @@ -21,19 +21,10 @@ DECLARE_GLOBAL_DATA_PTR; int board_phys_sdram_size(phys_size_t *size) { - const fdt64_t *val; - int offset; - int len; - - /* get size from dt which SPL updated per EEPROM config */ - offset = fdt_path_offset(gd->fdt_blob, "/memory"); - if (offset < 0) + if (!size) return -EINVAL; - val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); - if (len < sizeof(*val) * 2) - return -EINVAL; - *size = get_unaligned_be64(&val[1]); + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } |