video: Drop FSL DIU driver

This does not use driver model and is more than two years past the
migration date. Drop it.

It can be added back later if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>

5 files changed, 0 insertions, 315 deletions

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index c8f62bf..f13965d 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -44,8 +44,6 @@ ifndef CONFIG_RAMBOOT_PBL
 obj-$(CONFIG_FSL_FIXED_MMC_LOCATION)	+= sdhc_boot.o
 endif
 
-obj-$(CONFIG_FSL_DIU_CH7301)	+= diu_ch7301.o
-
 ifdef CONFIG_ARM
 obj-$(CONFIG_DEEP_SLEEP)		+= arm_sleep.o
 else
diff --git a/board/freescale/common/diu_ch7301.c b/board/freescale/common/diu_ch7301.c
deleted file mode 100644
index 05e6a3a..0000000
--- a/board/freescale/common/diu_ch7301.c
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2019 NXP
- * Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
- *	    Wang Dongsheng <dongsheng.wang@freescale.com>
- *
- * This file is copied and modified from the original t1040qds/diu.c.
- * Encoder can be used in T104x and LSx Platform.
- */
-
-#include <common.h>
-#include <stdio_dev.h>
-#include <i2c.h>
-#include <linux/delay.h>
-
-#define I2C_DVI_INPUT_DATA_FORMAT_REG		0x1F
-#define I2C_DVI_PLL_CHARGE_CNTL_REG		0x33
-#define I2C_DVI_PLL_DIVIDER_REG			0x34
-#define I2C_DVI_PLL_SUPPLY_CNTL_REG		0x35
-#define I2C_DVI_PLL_FILTER_REG			0x36
-#define I2C_DVI_TEST_PATTERN_REG		0x48
-#define I2C_DVI_POWER_MGMT_REG			0x49
-#define I2C_DVI_LOCK_STATE_REG			0x4D
-#define I2C_DVI_SYNC_POLARITY_REG		0x56
-
-/*
- * Set VSYNC/HSYNC to active high. This is polarity of sync signals
- * from DIU->DVI. The DIU default is active igh, so DVI is set to
- * active high.
- */
-#define I2C_DVI_INPUT_DATA_FORMAT_VAL		0x98
-
-#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL	0x06
-#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL	0x26
-#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL	0xA0
-#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL	0x08
-#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL	0x16
-#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL	0x60
-
-/* Clear test pattern */
-#define I2C_DVI_TEST_PATTERN_VAL		0x18
-/* Exit Power-down mode */
-#define I2C_DVI_POWER_MGMT_VAL			0xC0
-
-/* Monitor polarity is handled via DVI Sync Polarity Register */
-#define I2C_DVI_SYNC_POLARITY_VAL		0x00
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock)
-{
-	int ret;
-	u8 temp;
-
-	temp = I2C_DVI_TEST_PATTERN_VAL;
-#if CONFIG_IS_ENABLED(DM_I2C)
-	struct udevice *dev;
-
-	ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
-				      CONFIG_SYS_I2C_DVI_ADDR,
-				      1, &dev);
-	if (ret) {
-		printf("%s: Cannot find udev for a bus %d\n", __func__,
-		       CONFIG_SYS_I2C_DVI_BUS_NUM);
-		return ret;
-	}
-	ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#else
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select proper dvi test pattern\n");
-		return ret;
-	}
-	temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
-			1, &temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi input data format\n");
-		return ret;
-	}
-
-	/* Set Sync polarity register */
-	temp = I2C_DVI_SYNC_POLARITY_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi syc polarity\n");
-		return ret;
-	}
-
-	/* Set PLL registers based on pixel clock rate*/
-	if (pixclock > 65000000) {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1,	&temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	} else {
-		temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll charge_cntl\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll divider\n");
-			return ret;
-		}
-		temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
-		ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
-				I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
-		if (ret) {
-			puts("I2C: failed to select dvi pll filter\n");
-			return ret;
-		}
-	}
-
-	temp = I2C_DVI_POWER_MGMT_VAL;
-	ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
-			&temp, 1);
-	if (ret) {
-		puts("I2C: failed to select dvi power mgmt\n");
-		return ret;
-	}
-#endif
-
-	udelay(500);
-
-	return 0;
-}
diff --git a/board/freescale/common/diu_ch7301.h b/board/freescale/common/diu_ch7301.h
deleted file mode 100644
index f35661c..0000000
--- a/board/freescale/common/diu_ch7301.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#ifndef __DIU_HDMI_CH7301__
-#define __DIU_HDMI_CH7301__
-
-/* Programming of HDMI Chrontel CH7301 connector */
-int diu_set_dvi_encoder(unsigned int pixclock);
-
-#endif
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index d67e941..a949501 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -8,7 +8,6 @@ else
 obj-y	+= t104xrdb.o
 obj-y	+= cpld.o
 obj-y	+= eth.o
-obj-$(CONFIG_FSL_DIU_FB)+= diu.o
 endif
 obj-y	+= ddr.o
 obj-y	+= law.o
diff --git a/board/freescale/t104xrdb/diu.c b/board/freescale/t104xrdb/diu.c
deleted file mode 100644
index 022d329..0000000
--- a/board/freescale/t104xrdb/diu.c
+++ /dev/null
@@ -1,83 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
- */
-
-#include <clock_legacy.h>
-#include <asm/io.h>
-#include <common.h>
-#include <command.h>
-#include <fsl_diu_fb.h>
-#include <linux/ctype.h>
-
-#include "../common/diu_ch7301.h"
-
-#include "cpld.h"
-#include "t104xrdb.h"
-
-/*
- * DIU Area Descriptor
- *
- * Note that we need to byte-swap the value before it's written to the AD
- * register. So even though the registers don't look like they're in the same
- * bit positions as they are on the MPC8610, the same value is written to the
- * AD register on the MPC8610 and on the P1022.
- */
-#define AD_BYTE_F		0x10000000
-#define AD_ALPHA_C_SHIFT	25
-#define AD_BLUE_C_SHIFT		23
-#define AD_GREEN_C_SHIFT	21
-#define AD_RED_C_SHIFT		19
-#define AD_PIXEL_S_SHIFT	16
-#define AD_COMP_3_SHIFT		12
-#define AD_COMP_2_SHIFT		8
-#define AD_COMP_1_SHIFT		4
-#define AD_COMP_0_SHIFT		0
-
-void diu_set_pixel_clock(unsigned int pixclock)
-{
-	unsigned long speed_ccb, temp;
-	u32 pixval;
-	int ret;
-
-	speed_ccb = get_bus_freq(0);
-	temp = 1000000000 / pixclock;
-	temp *= 1000;
-	pixval = speed_ccb / temp;
-
-	/* Program HDMI encoder */
-	ret = diu_set_dvi_encoder(temp);
-	if (ret) {
-		puts("Failed to set DVI encoder\n");
-		return;
-	}
-
-	/* Program pixel clock */
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-
-	/* enable clock*/
-	out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
-		 ((pixval << PXCK_BITS_START) & PXCK_MASK));
-}
-
-int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
-{
-	u32 pixel_format;
-	u8 sw;
-
-	/*Configure Display ouput port as HDMI*/
-	sw = CPLD_READ(sfp_ctl_status);
-	CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
-
-	pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
-		(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
-		(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
-		(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
-		(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
-
-	printf("DIU: Switching to monitor DVI @ %ux%u\n",  xres, yres);
-
-	return fsl_diu_init(xres, yres, pixel_format, 0);
-}