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| author | Peng Fan <peng.fan@nxp.com> | 2023-01-31 16:42:33 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-03-29 20:15:43 +0200 |
| commit | 9b7e39b6c1ff40a8336328708727394ae8a107e5 (patch) | |
| tree | 2ff9fabace408c02db25f1c8c42908484a773556 /board/freescale | |
| parent | 6c01ca0a530689d45b2ff7d679bd653ad8adaeb4 (diff) | |
| download | u-boot-9b7e39b6c1ff40a8336328708727394ae8a107e5.zip u-boot-9b7e39b6c1ff40a8336328708727394ae8a107e5.tar.gz u-boot-9b7e39b6c1ff40a8336328708727394ae8a107e5.tar.bz2 | |
imx8ulp_evk: disable overflow of port0 for LPAV
Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/imx8ulp_evk/lpddr4_timing.c | 2 | ||||
| -rw-r--r-- | board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c index e9edb87..6d28053 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -396,7 +396,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0608e0, 0x30f0f }, /* 568 */ { 0x2e0608e4, 0xffffffff }, /* 569 */ { 0x2e0608e8, 0x32070f0f }, /* 570 */ - { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608ec, 0x1320000 }, /* 571 */ { 0x2e0608f0, 0x13200 }, /* 572 */ { 0x2e0608f4, 0x132 }, /* 573 */ { 0x2e0608fc, 0x1b1b0000 }, /* 575 */ diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c index 9728a25..7945760 100644 --- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c +++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c @@ -395,7 +395,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = { { 0x2e0608e0, 0x30f0f }, /* 568 */ { 0x2e0608e4, 0xffffffff }, /* 569 */ { 0x2e0608e8, 0x32070f0f }, /* 570 */ - { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608ec, 0x1320000 }, /* 571 */ { 0x2e0608f0, 0x13200 }, /* 572 */ { 0x2e0608f4, 0x132 }, /* 573 */ { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ |