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| author | Scott Wood <scottwood@freescale.com> | 2012-10-12 18:02:24 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2012-11-26 15:41:27 -0600 |
| commit | 13d1143ffb4dc0c71478534b6b52402e95be9420 (patch) | |
| tree | 0fb8cac0505d385547eb44f4c4afc35165ac7e62 /board/freescale/p1_p2_rdb_pc/spl_minimal.c | |
| parent | d674bccf738396ecdc4374f5b5cb3e7fd376a0ab (diff) | |
| download | u-boot-13d1143ffb4dc0c71478534b6b52402e95be9420.zip u-boot-13d1143ffb4dc0c71478534b6b52402e95be9420.tar.gz u-boot-13d1143ffb4dc0c71478534b6b52402e95be9420.tar.bz2 | |
powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot
This allows DDR configuration to be deferred to the final U-Boot image,
which is able to make use of SPD data. The SPL itself cannot use SPD due
to code size constraints. It previously used fixed register values for
DDR configuration, and those values did not work on the p2020rdb-pca
board I tested with. It's possible that different revisions of the board
require different settings. Using SPD eliminates that problem.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc/spl_minimal.c')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/spl_minimal.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 5c893ee..d48fb01 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -23,16 +23,18 @@ #include <ns16550.h> #include <asm/io.h> #include <nand.h> +#include <linux/compiler.h> #include <asm/fsl_law.h> #include <asm/fsl_ddr_sdram.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_SYS_INIT_L2_ADDR /* * Fixed sdram init -- doesn't use serial presence detect. */ -void sdram_init(void) +static void sdram_init(void) { ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; @@ -71,6 +73,7 @@ void sdram_init(void) set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); } +#endif void board_init_f(ulong bootflag) { @@ -101,8 +104,10 @@ void board_init_f(ulong bootflag) __raw_writel(0x00000000, &pgpio->gpdir); #endif +#ifndef CONFIG_SYS_INIT_L2_ADDR /* Initialize the DDR3 */ sdram_init(); +#endif /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before |