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| author | Ye Li <ye.li@nxp.com> | 2021-10-29 09:46:19 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:38 +0100 |
| commit | 829e06bf41757980a67e6f9bdd1b70189c0c8537 (patch) | |
| tree | ed32822cec0b6e0fd52355e8afd0592f66f67b96 /board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | |
| parent | 5ff18da34f915df28f2d20e1d72583d35947e858 (diff) | |
| download | u-boot-829e06bf41757980a67e6f9bdd1b70189c0c8537.zip u-boot-829e06bf41757980a67e6f9bdd1b70189c0c8537.tar.gz u-boot-829e06bf41757980a67e6f9bdd1b70189c0c8537.tar.bz2 | |
imx8ulp: clock: Add MIPI DSI clock and DCNano clock
Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg')
0 files changed, 0 insertions, 0 deletions