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| author | Zhao Qiang <B45475@freescale.com> | 2013-09-04 10:11:27 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:13:11 -0700 |
| commit | ffee1dde3c4cb2721c56c78e0360affec1c23d3f (patch) | |
| tree | fc87c859def7c217c5caca59a4a9ac3f0eae69bc /board/freescale/corenet_ds/eth_p4080.c | |
| parent | d56898249c09f8264fc398dd209c293116a293c9 (diff) | |
| download | u-boot-ffee1dde3c4cb2721c56c78e0360affec1c23d3f.zip u-boot-ffee1dde3c4cb2721c56c78e0360affec1c23d3f.tar.gz u-boot-ffee1dde3c4cb2721c56c78e0360affec1c23d3f.tar.bz2 | |
SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.
QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
1. Confirm whether QSGMII Riser Card is used.
2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.
However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Diffstat (limited to 'board/freescale/corenet_ds/eth_p4080.c')
| -rw-r--r-- | board/freescale/corenet_ds/eth_p4080.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 597d0cb..e5beb55 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -37,6 +37,9 @@ #define EMI1_MASK 0xc0000000 #define EMI2_MASK 0x30000000 +#define PHY_BASE_ADDR 0x00 +#define PHY_BASE_ADDR_SLOT5 0x10 + static int mdio_mux[NUM_FM_PORTS]; static char *mdio_names[16] = { @@ -290,6 +293,7 @@ int board_eth_init(bd_t *bis) int i; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; + struct mii_dev *bus; /* Initialize the mdio_mux array so we can recognize empty elements */ for (i = 0; i < NUM_FM_PORTS; i++) @@ -370,6 +374,9 @@ int board_eth_init(bd_t *bis) break; } } + bus = mii_dev_for_muxval(EMI1_SLOT5); + set_sgmii_phy(bus, FM1_DTSEC1, + CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5); for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { int idx = i - FM1_10GEC1, lane, slot; @@ -435,6 +442,11 @@ int board_eth_init(bd_t *bis) } } + bus = mii_dev_for_muxval(EMI1_SLOT3); + set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); + bus = mii_dev_for_muxval(EMI1_SLOT4); + set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR); + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { int idx = i - FM2_10GEC1, lane, slot; switch (fm_info_get_enet_if(i)) { |