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| author | Madalin Bucur <madalin.bucur@oss.nxp.com> | 2020-11-04 15:09:17 +0200 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2020-12-10 13:56:39 +0530 |
| commit | 848a2efd142ab6d879b1afed0cdbfada30522fa7 (patch) | |
| tree | 32ef8b42f1aed1b1ff610cea82df8d7a497bd824 /board/freescale/corenet_ds/eth_hydra.c | |
| parent | ccedd4ff8e359acfbf1877af14937a9e5045b25f (diff) | |
| download | u-boot-848a2efd142ab6d879b1afed0cdbfada30522fa7.zip u-boot-848a2efd142ab6d879b1afed0cdbfada30522fa7.tar.gz u-boot-848a2efd142ab6d879b1afed0cdbfada30522fa7.tar.bz2 | |
board: freescale: powerpc: add support for all RGMII modes
Make sure all RGMII internal delay modes are covered.
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'board/freescale/corenet_ds/eth_hydra.c')
| -rw-r--r-- | board/freescale/corenet_ds/eth_hydra.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 8112c12..6500c2f 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -350,6 +350,9 @@ void fdt_fixup_board_enet(void *fdt) } break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: @@ -449,6 +452,9 @@ int board_eth_init(struct bd_info *bis) miiphy_get_dev_by_name("HYDRA_SGMII_MDIO")); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_ID: /* * If DTSEC4 is RGMII, then it's routed via via EC1 to * the first on-board RGMII port. If DTSEC5 is RGMII, |