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| author | Roy Zang <tie-fei.zang@freescale.com> | 2011-10-28 13:15:36 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-11-08 08:18:16 -0600 |
| commit | afc52db2f76e0215411a916af46c578fcfd02a81 (patch) | |
| tree | a48a045455d0adfd07b9462ccee0c1540a56ee0e /board/freescale/corenet_ds/eth_hydra.c | |
| parent | 5721385b187b3154c7768e6c182501022f4e2e45 (diff) | |
| download | u-boot-afc52db2f76e0215411a916af46c578fcfd02a81.zip u-boot-afc52db2f76e0215411a916af46c578fcfd02a81.tar.gz u-boot-afc52db2f76e0215411a916af46c578fcfd02a81.tar.bz2 | |
powerpc/QorIQ: fix network frame manager TBI PHY address settings
TBI PHY address (TBIPA) register has been set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c
So remove the duplicate code on QorIQ frame manager Ethernet related
platforms, which include Hydra board, P4080DS board and P2041rdb board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/corenet_ds/eth_hydra.c')
| -rw-r--r-- | board/freescale/corenet_ds/eth_hydra.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index a7a5e13..962f380 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -377,7 +377,6 @@ void fdt_fixup_board_enet(void *fdt) int board_eth_init(bd_t *bis) { #ifdef CONFIG_FMAN_ENET - struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; struct tgec_mdio_info tgec_mdio_info; unsigned int i, slot; @@ -387,13 +386,6 @@ int board_eth_init(bd_t *bis) initialize_lane_to_slot(); - /* - * Set TBIPA on FM1@DTSEC1. This is needed for configurations - * where FM1@DTSEC1 isn't used directly, since it provides - * MDIO for other ports. - */ - out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE); - /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); |