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authorPrabhakar Kushwaha <prabhakar@freescale.com>2012-09-17 17:30:31 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 03:04:28 -0500
commit9f26fd7947a92a30f4eb68d4d0f60c1a73ab4280 (patch)
treea8839910dd96b8a6c0bd25ad9f1ebb7d6eca8cb1 /board/freescale/common/qixis.c
parent320d53da605d67b9d95622c5c6bfd5ac2c17ed58 (diff)
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board/freescale/common:QIXIS:Fix magic number usage
QIXIS FPGA layout defines the address of registers but The actual register bit implementation is board-specific, So avoid use of magic numbers as it may vary across different boards's QIXIS FPGA implementation. Also, Avoid board specific defines in common/qixis.h Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/common/qixis.c')
-rw-r--r--board/freescale/common/qixis.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 6cd7e51..e336b32 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -32,22 +32,22 @@ void qixis_write(unsigned int reg, u8 value)
void qixis_reset(void)
{
- QIXIS_WRITE(rst_ctl, 0x83);
+ QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET);
}
void qixis_bank_reset(void)
{
- QIXIS_WRITE(rcfg_ctl, 0x20);
- QIXIS_WRITE(rcfg_ctl, 0x21);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
+ QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
}
-/* Set the boot bank to the power-on default bank0 */
+/* Set the boot bank to the power-on default bank */
void clear_altbank(void)
{
u8 reg;
reg = QIXIS_READ(brdcfg[0]);
- reg = reg & ~QIXIS_LBMAP_MASK;
+ reg = (reg & ~QIXIS_LBMAP_MASK) | QIXIS_LBMAP_DFLTBANK;
QIXIS_WRITE(brdcfg[0], reg);
}
@@ -115,7 +115,8 @@ int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
for (i = 0; i < ARRAY_SIZE(period); i++) {
if (strcmp(argv[2], period[i]) == 0) {
/* disable watchdog */
- QIXIS_WRITE(rcfg_ctl, rcfg & ~0x08);
+ QIXIS_WRITE(rcfg_ctl,
+ rcfg & ~QIXIS_RCFG_CTL_WATCHDOG_ENBLE);
QIXIS_WRITE(watch, ((i<<2) - 1));
QIXIS_WRITE(rcfg_ctl, rcfg);
return 0;