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| author | Kumar Gala <galak@kernel.crashing.org> | 2011-08-30 17:40:11 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-09-29 19:01:06 -0500 |
| commit | f8bc7bb5a79b392db3af9f62b63caefab8afbc31 (patch) | |
| tree | 9ee756eebfdcab351f4a00a52fa4505b5e2f0feb /board/freescale/common/p_corenet | |
| parent | 360275b362e50f480b09c7c8770019ea4287afad (diff) | |
| download | u-boot-f8bc7bb5a79b392db3af9f62b63caefab8afbc31.zip u-boot-f8bc7bb5a79b392db3af9f62b63caefab8afbc31.tar.gz u-boot-f8bc7bb5a79b392db3af9f62b63caefab8afbc31.tar.bz2 | |
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.
The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/common/p_corenet')
| -rw-r--r-- | board/freescale/common/p_corenet/law.c | 5 | ||||
| -rw-r--r-- | board/freescale/common/p_corenet/tlb.c | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 58f23c5..09ef561 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -35,7 +35,12 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_QMAN_MEM_PHYS SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), #endif +#ifdef PIXIS_BASE_PHYS SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif +#ifdef CPLD_BASE_PHYS + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS /* Limit DCSR to 32M to access NPC Trace Buffer */ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 5e48d6c..6a0026a 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -44,10 +44,17 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), +#ifdef CPLD_BASE + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), +#endif +#ifdef PIXIS_BASE SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), +#endif /* TLB 1 */ /* *I*** - Covers boot page */ |