arm: Remove cm_t335 board

This board is behind on several mandatory DM migrations and is missing
OF_CONTROL support that makes other conversions impossible. Remove it.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Tom Rini <trini@konsulko.com>

7 files changed, 0 insertions, 537 deletions

diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
deleted file mode 100644
index 683efde..0000000
--- a/board/compulab/cm_t335/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_CM_T335
-
-config SYS_BOARD
-	default "cm_t335"
-
-config SYS_VENDOR
-	default "compulab"
-
-config SYS_SOC
-	default "am33xx"
-
-config SYS_CONFIG_NAME
-	default "cm_t335"
-
-endif
diff --git a/board/compulab/cm_t335/MAINTAINERS b/board/compulab/cm_t335/MAINTAINERS
deleted file mode 100644
index 5fb922c..0000000
--- a/board/compulab/cm_t335/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-CM_T335 BOARD
-M:	Igor Grinberg <grinberg@compulab.co.il>
-S:	Maintained
-F:	board/compulab/cm_t335/
-F:	include/configs/cm_t335.h
-F:	configs/cm_t335_defconfig
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
deleted file mode 100644
index 34f6713..0000000
--- a/board/compulab/cm_t335/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
-#
-# Author: Ilya Ledvich <ilya@compulab.co.il>
-
-obj-y	+= cm_t335.o
-obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
deleted file mode 100644
index 1d4a3ac..0000000
--- a/board/compulab/cm_t335/cm_t335.c
+++ /dev/null
@@ -1,166 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board functions for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <env.h>
-#include <errno.h>
-#include <miiphy.h>
-#include <net.h>
-#include <status_led.h>
-#include <cpsw.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware_am33xx.h>
-#include <asm/io.h>
-#include <asm/gpio.h>
-
-#include "../common/eeprom.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	gpmc_init();
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
-	status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
-#endif
-	return 0;
-}
-
-#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slave = {
-	.slave_reg_ofs	= 0x208,
-	.sliver_reg_ofs	= 0xd80,
-	.phy_addr	= 0,
-	.phy_if		= PHY_INTERFACE_MODE_RGMII,
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= CPSW_MDIO_BASE,
-	.cpsw_base		= CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= &cpsw_slave,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.bd_ram_ofs		= 0x2000,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-/* PHY reset GPIO */
-#define GPIO_PHY_RST		GPIO_PIN(3, 7)
-
-static void board_phy_init(void)
-{
-	gpio_request(GPIO_PHY_RST, "phy_rst");
-	gpio_direction_output(GPIO_PHY_RST, 0);
-	mdelay(2);
-	gpio_set_value(GPIO_PHY_RST, 1);
-	mdelay(2);
-}
-
-static void get_efuse_mac_addr(uchar *enetaddr)
-{
-	uint32_t mac_hi, mac_lo;
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-	mac_lo = readl(&cdev->macid0l);
-	mac_hi = readl(&cdev->macid0h);
-	enetaddr[0] = mac_hi & 0xFF;
-	enetaddr[1] = (mac_hi & 0xFF00) >> 8;
-	enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
-	enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
-	enetaddr[4] = mac_lo & 0xFF;
-	enetaddr[5] = (mac_lo & 0xFF00) >> 8;
-}
-
-/*
- * Routine: handle_mac_address
- * Description: prepare MAC address for on-board Ethernet.
- */
-static int handle_mac_address(void)
-{
-	uchar enetaddr[6];
-	int rv;
-
-	rv = eth_env_get_enetaddr("ethaddr", enetaddr);
-	if (rv)
-		return 0;
-
-	rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
-	if (rv)
-		get_efuse_mac_addr(enetaddr);
-
-	if (!is_valid_ethaddr(enetaddr))
-		return -1;
-
-	return eth_env_set_enetaddr("ethaddr", enetaddr);
-}
-
-#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
-#define AR8051_PHY_DEBUG_DATA_REG	0x1e
-#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
-#define AR8051_RGMII_TX_CLK_DLY		0x100
-
-int board_eth_init(struct bd_info *bis)
-{
-	int rv, n = 0;
-	const char *devname;
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-	rv = handle_mac_address();
-	if (rv)
-		printf("No MAC address found!\n");
-
-	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
-
-	board_phy_init();
-
-	rv = cpsw_register(&cpsw_data);
-	if (rv < 0)
-		printf("Error %d registering CPSW switch\n", rv);
-	else
-		n += rv;
-
-	/*
-	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
-	 * operating points.  So we must set the TX clock delay feature
-	 * in the AR8051 PHY.  Since we only support a single ethernet
-	 * device, we only do this for the first instance.
-	 */
-	devname = miiphy_get_current_dev();
-
-	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
-		     AR8051_DEBUG_RGMII_CLK_DLY_REG);
-	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
-		     AR8051_RGMII_TX_CLK_DLY);
-	return n;
-}
-#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
deleted file mode 100644
index 1c326bd..0000000
--- a/board/compulab/cm_t335/mux.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Pinmux configuration for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-
-static struct module_pin_mux uart0_pin_mux[] = {
-	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
-	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
-	{-1},
-};
-
-static struct module_pin_mux uart1_pin_mux[] = {
-	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
-	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
-	{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
-	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
-	{-1},
-};
-
-static struct module_pin_mux mmc0_pin_mux[] = {
-	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
-	{-1},
-};
-
-static struct module_pin_mux i2c0_pin_mux[] = {
-	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
-	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
-	{-1},
-};
-
-static struct module_pin_mux i2c1_pin_mux[] = {
-	/* I2C_DATA */
-	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
-	/* I2C_SCLK */
-	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
-	{-1},
-};
-
-static struct module_pin_mux rgmii1_pin_mux[] = {
-	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
-	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
-	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
-	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
-	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
-	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
-	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
-	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
-	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
-	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
-	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
-	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
-	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
-	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
-	{-1},
-};
-
-static struct module_pin_mux nand_pin_mux[] = {
-	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
-	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
-	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
-	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
-	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
-	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
-	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
-	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
-	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
-	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
-	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
-	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
-	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
-	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
-	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
-	{-1},
-};
-
-static struct module_pin_mux eth_phy_rst_pin_mux[] = {
-	{OFFSET(emu0), (MODE(7) | PULLUDDIS)},	/* GPIO3_7 */
-	{-1},
-};
-
-static struct module_pin_mux status_led_pin_mux[] = {
-	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)},	/* GPIO2_0 */
-	{-1},
-};
-
-void set_uart_mux_conf(void)
-{
-	configure_module_pin_mux(uart0_pin_mux);
-	configure_module_pin_mux(uart1_pin_mux);
-}
-
-void set_mux_conf_regs(void)
-{
-	configure_module_pin_mux(i2c0_pin_mux);
-	configure_module_pin_mux(i2c1_pin_mux);
-	configure_module_pin_mux(rgmii1_pin_mux);
-	configure_module_pin_mux(eth_phy_rst_pin_mux);
-	configure_module_pin_mux(mmc0_pin_mux);
-	configure_module_pin_mux(nand_pin_mux);
-	configure_module_pin_mux(status_led_pin_mux);
-}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
deleted file mode 100644
index 33264df..0000000
--- a/board/compulab/cm_t335/spl.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * SPL specific code for Compulab CM-T335 board
- *
- * Board functions for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <ilya@compulab.co.il>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <errno.h>
-#include <init.h>
-#include <log.h>
-
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clocks_am33xx.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware_am33xx.h>
-#include <linux/sizes.h>
-
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0		= MT41J128MJT125_RD_DQS,
-	.datawdsratio0		= MT41J128MJT125_WR_DQS,
-	.datafwsratio0		= MT41J128MJT125_PHY_FIFO_WE,
-	.datawrsratio0		= MT41J128MJT125_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio		= MT41J128MJT125_RATIO,
-	.cmd0iclkout		= MT41J128MJT125_INVERT_CLKOUT,
-
-	.cmd1csratio		= MT41J128MJT125_RATIO,
-	.cmd1iclkout		= MT41J128MJT125_INVERT_CLKOUT,
-
-	.cmd2csratio		= MT41J128MJT125_RATIO,
-	.cmd2iclkout		= MT41J128MJT125_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config		= MT41J128MJT125_EMIF_SDCFG,
-	.ref_ctrl		= MT41J128MJT125_EMIF_SDREF,
-	.sdram_tim1		= MT41J128MJT125_EMIF_TIM1,
-	.sdram_tim2		= MT41J128MJT125_EMIF_TIM2,
-	.sdram_tim3		= MT41J128MJT125_EMIF_TIM3,
-	.zq_config		= MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1	= MT41J128MJT125_EMIF_READ_LATENCY |
-					PHY_EN_DYN_PWRDN,
-};
-
-const struct dpll_params dpll_ddr = {
-/*       M           N            M2  M3  M4  M5  M6 */
-	303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
-	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-	/* Get the frequency */
-	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
-	/* Set CORE Frequencies to OPP100 */
-	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
-	/* Set MPU Frequency to what we detected now that voltages are set */
-	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
-static void probe_sdram_size(long size)
-{
-	switch (size) {
-	case SZ_512M:
-		ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
-		break;
-	case SZ_256M:
-		ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
-		break;
-	case SZ_128M:
-		ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
-		break;
-	default:
-		puts("Failed configuring DRAM, resetting...\n\n");
-		reset_cpu();
-	}
-	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
-	config_ddr(303, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-
-void sdram_init(void)
-{
-	long size = SZ_1G;
-
-	do {
-		size = size / 2;
-		probe_sdram_size(size);
-	} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
-
-	return;
-}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
deleted file mode 100644
index 4993880..0000000
--- a/board/compulab/cm_t335/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.__image_copy_start)
-		*(.vectors)
-		CPUDIR/start.o (.text*)
-		board/compulab/cm_t335/built-in.o (.text*)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-
-	. = .;
-
-	. = ALIGN(4);
-	__u_boot_list : {
-		KEEP(*(SORT(__u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-
-	.image_copy_end :
-	{
-		*(.__image_copy_end)
-	}
-
-	.rel_dyn_start :
-	{
-		*(.__rel_dyn_start)
-	}
-
-	.rel.dyn : {
-		*(.rel*)
-	}
-
-	.rel_dyn_end :
-	{
-		*(.__rel_dyn_end)
-	}
-
-	.hash : { *(.hash*) }
-
-	.end :
-	{
-		*(.__end)
-	}
-
-	_image_binary_end = .;
-
-	/*
-	 * Deprecated: this MMU section is used by pxa at present but
-	 * should not be used by new boards/CPUs.
-	 */
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		 . = ALIGN(4);
-		 __bss_limit = .;
-	}
-
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	.dynsym _image_binary_end : { *(.dynsym) }
-	.dynbss : { *(.dynbss) }
-	.dynstr : { *(.dynstr*) }
-	.dynamic : { *(.dynamic*) }
-	.plt : { *(.plt*) }
-	.interp : { *(.interp*) }
-	.gnu : { *(.gnu*) }
-	.ARM.exidx : { *(.ARM.exidx*) }
-}