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| author | Andre Przywara <andre.przywara@arm.com> | 2022-03-04 16:30:16 +0000 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-01 14:59:15 -0400 |
| commit | 30cacb8123459328c46c25f65196bb4885dcdb05 (patch) | |
| tree | 08989d77f9d77eca24b39c972d68368ef28f89e8 /board/armltd/vexpress64/vexpress64.c | |
| parent | 168e815d258c410e191107bceecc426557474be2 (diff) | |
| download | u-boot-30cacb8123459328c46c25f65196bb4885dcdb05.zip u-boot-30cacb8123459328c46c25f65196bb4885dcdb05.tar.gz u-boot-30cacb8123459328c46c25f65196bb4885dcdb05.tar.bz2 | |
vexpress64: generalise page table generation
In preparation for the ARMv8-R64 FVP support, which has DRAM mapped at
0x0, generalise the page table generation, by using symbolic names for
the address ranges instead of fixed numbers.
We already define the base of the DRAM and MMIO regions, so just use
those symbols in the page table description. Rename V2M_BASE to the more
speaking V2M_DRAM_BASE on the way.
On the VExpress memory map, the address space right after 4GB is of no
particular interest to software, as the whole of DRAM is mapped at 32GB
instead. The first 2 GB alias to the lower 2GB of DRAM mapped below 4GB,
so we skip this part and map some more of the high DRAM, should anyone
need it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'board/armltd/vexpress64/vexpress64.c')
| -rw-r--r-- | board/armltd/vexpress64/vexpress64.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7d5e551..c3ad1fc 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -15,6 +15,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <linux/compiler.h> +#include <linux/sizes.h> #include <dm/platform_data/serial_pl01x.h> #include "pcie.h" #include <asm/armv8/mmu.h> @@ -38,16 +39,27 @@ U_BOOT_DRVINFO(vexpress_serials) = { static struct mm_region vexpress64_mem_map[] = { { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, + .virt = V2M_PA_BASE, + .phys = V2M_PA_BASE, + .size = SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0xff80000000UL, + .virt = V2M_DRAM_BASE, + .phys = V2M_DRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* + * DRAM beyond 2 GiB is located high. Let's map just some + * of it, although U-Boot won't realistically use it, and + * the actual available amount might be smaller on the model. + */ + .virt = 0x880000000UL, /* 32 + 2 GiB */ + .phys = 0x880000000UL, + .size = 6UL * SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { |