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authorConor Dooley <conor.dooley@microchip.com>2022-10-25 08:58:47 +0100
committerLeo Yu-Chi Liang <ycliang@andestech.com>2022-11-15 15:37:17 +0800
commit88b697fb37432b95bd87525e718726607bdb2123 (patch)
treeb406040e16430ac1a14adc107b4f518847328d28 /board/BuR/brxre1
parent32cfdd51630506393ca078aa36fa70248d549109 (diff)
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clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI clock as their parent & the mtimer clock is derived from the external reference clock directly. Stop assuming the AHB clock to be the parent of all "periph" clocks and define their correct parents instead. Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
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