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| author | Michal Simek <michal.simek@xilinx.com> | 2022-02-23 16:17:38 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2022-03-07 16:33:47 +0100 |
| commit | 59e1bdd48d059563287a4424f3d6ef9218c49581 (patch) | |
| tree | 69e0c48348aeefe300530cc4603d5fbe08d18396 /arch | |
| parent | c36dc2449b1f902aed49548b4f058ec51ec42f08 (diff) | |
| download | u-boot-59e1bdd48d059563287a4424f3d6ef9218c49581.zip u-boot-59e1bdd48d059563287a4424f3d6ef9218c49581.tar.gz u-boot-59e1bdd48d059563287a4424f3d6ef9218c49581.tar.bz2 | |
arm64: zynqmp: Setup clock for DP and DPDMA
Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 2 |
3 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 664e658..86b9907 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -279,10 +279,14 @@ &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; + assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ }; &zynqmp_dpsub { clocks = <&zynqmp_clk TOPSW_LSBUS>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; + assigned-clocks = <&zynqmp_clk DP_STC_REF>, + <&zynqmp_clk DP_AUDIO_REF>, + <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 22602d8..34fb592 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -115,10 +115,12 @@ status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 01b14eb..35247b0 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -95,10 +95,12 @@ status = "disabled"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; }; &zynqmp_dpdma { status = "okay"; + assigned-clock-rates = <600000000>; }; &usb0 { |