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| author | Siew Chin Lim <elly.siew.chin.lim@intel.com> | 2021-08-10 11:26:31 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2021-08-25 12:54:37 +0800 |
| commit | d694c7d46b052b8186be99876ba30cc1e469a01b (patch) | |
| tree | accb63a46cd76f60d14e680065a7c3e1015e4a7a /arch | |
| parent | 05e1e3befa380c1f4114bfbd877b0b8ca334a5e9 (diff) | |
| download | u-boot-d694c7d46b052b8186be99876ba30cc1e469a01b.zip u-boot-d694c7d46b052b8186be99876ba30cc1e469a01b.tar.gz u-boot-d694c7d46b052b8186be99876ba30cc1e469a01b.tar.bz2 | |
arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index f8d3d48..9c19157 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void) #ifdef CONFIG_TARGET_SOCFPGA_AGILEX ret = socfpga_get_base_addr("intel,agilex-clkmgr", &socfpga_clkmgr_base); +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + ret = socfpga_get_base_addr("intel,n5x-clkmgr", + &socfpga_clkmgr_base); #else ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); #endif |