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author | Tom Rini <trini@konsulko.com> | 2019-01-15 22:05:05 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2019-01-15 22:05:05 -0500 |
commit | 0cd35f392000fb0783149d9b5f66c5f2e01bcbf1 (patch) | |
tree | b2bc80bd79b2ba7aa387abc575630b03b7470c36 /arch | |
parent | e807f6b5f9a164dc1fc35e1c733fa343acf335c0 (diff) | |
parent | 91882c472d8c0aef4db699d3f2de55bf43d4ae4b (diff) | |
download | u-boot-0cd35f392000fb0783149d9b5f66c5f2e01bcbf1.zip u-boot-0cd35f392000fb0783149d9b5f66c5f2e01bcbf1.tar.gz u-boot-0cd35f392000fb0783149d9b5f66c5f2e01bcbf1.tar.bz2 |
Merge git://git.denx.de/u-boot-riscv
1. Improve cache implementation.
2. Fix and improve standalone applications
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv/config.mk | 3 | ||||
-rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 22 | ||||
-rw-r--r-- | arch/riscv/lib/cache.c | 14 | ||||
-rw-r--r-- | arch/riscv/lib/interrupts.c | 3 |
4 files changed, 31 insertions, 11 deletions
diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index ff4fe64..84654eb 100644 --- a/arch/riscv/config.mk +++ b/arch/riscv/config.mk @@ -23,8 +23,7 @@ PLATFORM_LDFLAGS += -m $(64bit-emul) EFI_LDS := elf_riscv64_efi.lds endif -CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 -LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/riscv.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_CPPFLAGS += -ffixed-gp -fpic PLATFORM_RELFLAGS += -fno-common -gdwarf-2 -ffunction-sections \ diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae17..228fc55 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@ #include <common.h> +void flush_dcache_all(void) +{ + /* + * Andes' AX25 does not have a coherence agent. U-Boot must use data + * cache flush and invalidate functions to keep data in the system + * coherent. + * The implementation of the fence instruction in the AX25 flushes the + * data cache and is used for this purpose. + */ + asm volatile ("fence" ::: "memory"); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c607..5437a12 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void) @@ -42,8 +40,8 @@ void cache_flush(void) void flush_cache(unsigned long addr, unsigned long size) { - invalidate_icache_all(); - flush_dcache_all(); + invalidate_icache_range(addr, addr + size); + flush_dcache_range(addr, addr + size); } __weak void icache_enable(void) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e185933..74c1e56 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -37,7 +37,8 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs) printf("exception code: %ld , %s , epc %lx , ra %lx\n", code, exception_code[code], epc, regs->ra); } else { - printf("Reserved\n"); + printf("reserved exception code: %ld , epc %lx , ra %lx\n", + code, epc, regs->ra); } hang(); |