Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxiWIP/30Jan2022

a bit delayed, the first batch of the sunxi pull request for this cycle.
This is mostly collecting some patches that were lying around for a
while, plus some recent fixes. Nothing too exciting at this point, but
of course they should be merged nevertheless.
There is the much bigger F1C100s SoC support coming up, which I hope to
be able to send in the next few days, along with the removal of sunxi's
lowlevel_init usage.

Compile tested for all 159 sunxi boards, plus briefly tested on BananaPi
M1, OrangePi Zero, Pine64 and Pine-H64.

4 files changed, 36 insertions, 16 deletions

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f3ab1ae..106605a 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -226,8 +226,10 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
-int sunxi_gpio_set_drv(u32 pin, u32 val);
-int sunxi_gpio_set_pull(u32 pin, u32 val);
+void sunxi_gpio_set_drv(u32 pin, u32 val);
+void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val);
+void sunxi_gpio_set_pull(u32 pin, u32 val);
+void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 int sunxi_name_to_gpio(const char *name);
 
 #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 2c18cf0..d7f9a03 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -785,6 +785,16 @@ config AXP_GPIO
 	---help---
 	Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 
+config AXP_DISABLE_BOOT_ON_POWERON
+	bool "Disable device boot on power plug-in"
+	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default n
+	---help---
+	  Say Y here to prevent the device from booting up because of a plug-in
+	  event. When set, the device will boot into the SPL briefly to
+	  determine why it was powered on, and if it was determined because of
+	  a plug-in event instead of a button press event it will shut back off.
+
 config VIDEO_SUNXI
 	bool "Enable graphical uboot console on HDMI, LCD or VGA"
 	depends on !MACH_SUN8I_A83T
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c
index acdfb3c..83e8abc 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
@@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para)
 			}
 		}
 
-		setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
+		clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
 	}
 
 	clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
@@ -720,7 +720,7 @@ static bool mctl_phy_init(struct dram_para *para)
 	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc);
 	writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
 
-	if (IS_ENABLED(DRAM_ODT_EN))
+	if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 		mctl_phy_configure_odt();
 
 	clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c
index 642483f..c95fcee 100644
--- a/arch/arm/mach-sunxi/pinmux.c
+++ b/arch/arm/mach-sunxi/pinmux.c
@@ -14,7 +14,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
 	u32 index = GPIO_CFG_INDEX(bank_offset);
 	u32 offset = GPIO_CFG_OFFSET(bank_offset);
 
-	clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
+	clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset);
 }
 
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
@@ -31,7 +31,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
 	u32 offset = GPIO_CFG_OFFSET(bank_offset);
 	u32 cfg;
 
-	cfg = readl(&pio->cfg[0] + index);
+	cfg = readl(&pio->cfg[index]);
 	cfg >>= offset;
 
 	return cfg & 0xf;
@@ -45,26 +45,34 @@ int sunxi_gpio_get_cfgpin(u32 pin)
 	return sunxi_gpio_get_cfgbank(pio, pin);
 }
 
-int sunxi_gpio_set_drv(u32 pin, u32 val)
+void sunxi_gpio_set_drv(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_DRV_INDEX(pin);
-	u32 offset = GPIO_DRV_OFFSET(pin);
 	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
-	clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
+	sunxi_gpio_set_drv_bank(pio, pin, val);
+}
+
+void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val)
+{
+	u32 index = GPIO_DRV_INDEX(bank_offset);
+	u32 offset = GPIO_DRV_OFFSET(bank_offset);
 
-	return 0;
+	clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset);
 }
 
-int sunxi_gpio_set_pull(u32 pin, u32 val)
+void sunxi_gpio_set_pull(u32 pin, u32 val)
 {
 	u32 bank = GPIO_BANK(pin);
-	u32 index = GPIO_PULL_INDEX(pin);
-	u32 offset = GPIO_PULL_OFFSET(pin);
 	struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
 
-	clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
+	sunxi_gpio_set_pull_bank(pio, pin, val);
+}
+
+void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val)
+{
+	u32 index = GPIO_PULL_INDEX(bank_offset);
+	u32 offset = GPIO_PULL_OFFSET(bank_offset);
 
-	return 0;
+	clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset);
 }