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| author | Suman Anna <s-anna@ti.com> | 2019-09-04 16:01:41 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-11 10:07:35 -0400 |
| commit | 35f21c3ac649daad3f322d4d556c8ee7683c6ffd (patch) | |
| tree | b3cf2690e656d714b3b93114856f584ab9c75de8 /arch | |
| parent | 1b846fc24d80ceb358312b4aa3e8242d36784fe4 (diff) | |
| download | u-boot-35f21c3ac649daad3f322d4d556c8ee7683c6ffd.zip u-boot-35f21c3ac649daad3f322d4d556c8ee7683c6ffd.tar.gz u-boot-35f21c3ac649daad3f322d4d556c8ee7683c6ffd.tar.bz2 | |
arm: dts: k3-am65-mcu: Add MCU domain R5F DT nodes
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor
subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster
can be configured at boot time to be either run in a LockStep mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/k3-am65-mcu.dtsi | 40 | ||||
| -rw-r--r-- | arch/arm/dts/k3-am654-base-board.dts | 5 |
2 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm/dts/k3-am65-mcu.dtsi b/arch/arm/dts/k3-am65-mcu.dtsi index c9bfd9b..c42e755 100644 --- a/arch/arm/dts/k3-am65-mcu.dtsi +++ b/arch/arm/dts/k3-am65-mcu.dtsi @@ -2,7 +2,7 @@ /* * Device Tree Source for AM6 SoC Family MCU Domain peripherals * - * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ */ &cbass_mcu { @@ -26,4 +26,42 @@ clocks = <&k3_clks 114 1>; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,am654-r5fss"; + lockstep-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,am654-r5f"; + reg = <0x41000000 0x00008000>, + <0x41010000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <159>; + ti,sci-proc-ids = <0x01 0xFF>; + resets = <&k3_reset 159 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,am654-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x02 0xFF>; + resets = <&k3_reset 245 1>; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; }; diff --git a/arch/arm/dts/k3-am654-base-board.dts b/arch/arm/dts/k3-am654-base-board.dts index e73b9aa..573ead0 100644 --- a/arch/arm/dts/k3-am654-base-board.dts +++ b/arch/arm/dts/k3-am654-base-board.dts @@ -17,6 +17,11 @@ bootargs = "earlycon=ns16550a,mmio32,0x02800000"; }; + aliases { + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &mcu_r5fss0_core1; + }; + memory@80000000 { device_type = "memory"; /* 4G RAM */ |