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author | Tom Rini <trini@konsulko.com> | 2022-01-20 12:40:20 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2022-01-20 12:40:20 -0500 |
commit | 2d7a463e82daeba4f6a7fb59bac0fe94d6f6d3a2 (patch) | |
tree | 96e28ce689933dd4ebd120309a9caa2e02897d48 /arch | |
parent | 3918376e91dac7711cf04bd06f8de80e797edfea (diff) | |
parent | 8f880c3d89432e9988b23bb7099d6360c14a206f (diff) | |
download | u-boot-2d7a463e82daeba4f6a7fb59bac0fe94d6f6d3a2.zip u-boot-2d7a463e82daeba4f6a7fb59bac0fe94d6f6d3a2.tar.gz u-boot-2d7a463e82daeba4f6a7fb59bac0fe94d6f6d3a2.tar.bz2 |
Merge https://source.denx.de/u-boot/custodians/u-boot-marvellWIP/20Jan2022
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro
(Marek)
- turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali)
- pci_mvebu: Add support for Kirkwood PCIe controllers (Pali)
- SPL: More verifications for kwbimage in SPL (Pali)
- mvebu: Remove comphy_update_map() (Pali)
- Minor misc stuff
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 9 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/cpu.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/cpu.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/spl.c | 133 | ||||
-rw-r--r-- | arch/arm/mach-sunxi/spl_spi_sunxi.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-tegra/gpu.c | 5 | ||||
-rw-r--r-- | arch/mips/mach-octeon/octeon_fdt.c | 11 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc85xx/liodn.c | 9 |
9 files changed, 107 insertions, 74 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 4354aa2..2fa7ebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -161,14 +161,9 @@ void fsl_fdt_disable_usb(void *blob) * controller is used, SYSCLK must meet the additional requirement * of 100 MHz. */ - if (get_board_sys_clk() != 100000000) { - off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); - while (off != -FDT_ERR_NOTFOUND) { + if (get_board_sys_clk() != 100000000) + fdt_for_each_node_by_compatible(off, blob, -1, "snps,dwc3") fdt_status_disabled(blob, off); - off = fdt_node_offset_by_compatible(blob, off, - "snps,dwc3"); - } - } } #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 82c5a8b..25cd82f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -116,8 +116,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph, int noff, len, icid; const u32 *prop; - noff = fdt_node_offset_by_compatible(blob, -1, compat); - while (noff > 0) { + fdt_for_each_node_by_compatible(noff, blob, -1, compat) { prop = fdt_getprop(blob, noff, "cell-index", &len); if (!prop) { printf("WARNING missing cell-index for fman port\n"); @@ -137,8 +136,6 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph, } fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1); - - noff = fdt_node_offset_by_compatible(blob, noff, compat); } } diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index e957129..80f893a 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -54,11 +54,11 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) static struct mbus_win windows[] = { /* Window 0: PCIE MEM address space */ - { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, + { KW_DEFADR_PCI_MEM, KW_DEFADR_PCI_MEM_SIZE, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, /* Window 1: PCIE IO address space */ - { KW_DEFADR_PCI_IO, 1024 * 64, + { KW_DEFADR_PCI_IO, KW_DEFADR_PCI_IO_SIZE, KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, /* Window 2: NAND Flash address space */ diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index ea42182..71c546f 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -68,6 +68,9 @@ enum kwcpu_attrib { #define KW_DEFADR_SPIF 0xE8000000 #define KW_DEFADR_BOOTROM 0xF8000000 +#define KW_DEFADR_PCI_MEM_SIZE (1024 * 1024 * 256) +#define KW_DEFADR_PCI_IO_SIZE (1024 * 64) + struct mbus_win { u32 base; u32 size; diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index aada83f..273ecb8 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -46,7 +46,8 @@ #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) && CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR != 0 #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR must be set to 0 #endif -#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) && CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 +#if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET) && \ + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET != 0 #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET must be set to 0 #endif #endif @@ -57,7 +58,8 @@ * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper. */ #ifdef CONFIG_SPL_SATA -#if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 +#if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || \ + !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1 #endif #endif @@ -73,23 +75,23 @@ /* Structure of the main header, version 1 (Armada 370/XP/375/38x/39x) */ struct kwbimage_main_hdr_v1 { - uint8_t blockid; /* 0x0 */ - uint8_t flags; /* 0x1 */ - uint16_t nandpagesize; /* 0x2-0x3 */ - uint32_t blocksize; /* 0x4-0x7 */ - uint8_t version; /* 0x8 */ - uint8_t headersz_msb; /* 0x9 */ - uint16_t headersz_lsb; /* 0xA-0xB */ - uint32_t srcaddr; /* 0xC-0xF */ - uint32_t destaddr; /* 0x10-0x13 */ - uint32_t execaddr; /* 0x14-0x17 */ - uint8_t options; /* 0x18 */ - uint8_t nandblocksize; /* 0x19 */ - uint8_t nandbadblklocation; /* 0x1A */ - uint8_t reserved4; /* 0x1B */ - uint16_t reserved5; /* 0x1C-0x1D */ - uint8_t ext; /* 0x1E */ - uint8_t checksum; /* 0x1F */ + u8 blockid; /* 0x0 */ + u8 flags; /* 0x1 */ + u16 nandpagesize; /* 0x2-0x3 */ + u32 blocksize; /* 0x4-0x7 */ + u8 version; /* 0x8 */ + u8 headersz_msb; /* 0x9 */ + u16 headersz_lsb; /* 0xA-0xB */ + u32 srcaddr; /* 0xC-0xF */ + u32 destaddr; /* 0x10-0x13 */ + u32 execaddr; /* 0x14-0x17 */ + u8 options; /* 0x18 */ + u8 nandblocksize; /* 0x19 */ + u8 nandbadblklocation; /* 0x1A */ + u8 reserved4; /* 0x1B */ + u16 reserved5; /* 0x1C-0x1D */ + u8 ext; /* 0x1E */ + u8 checksum; /* 0x1F */ } __packed; #ifdef CONFIG_SPL_MMC @@ -99,7 +101,35 @@ u32 spl_mmc_boot_mode(const u32 boot_device) } #endif +static u32 checksum32(void *start, u32 len) +{ + u32 csum = 0; + u32 *p = start; + + while (len > 0) { + csum += *p++; + len -= sizeof(u32); + }; + + return csum; +} + +int spl_check_board_image(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev) +{ + u32 csum = *(u32 *)(spl_image->load_addr + spl_image->size - 4); + + if (checksum32((void *)spl_image->load_addr, + spl_image->size - 4) != csum) { + printf("ERROR: Invalid data checksum in kwbimage\n"); + return -EINVAL; + } + + return 0; +} + int spl_parse_board_header(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, const void *image_header, size_t size) { const struct kwbimage_main_hdr_v1 *mhdr = image_header; @@ -116,51 +146,74 @@ int spl_parse_board_header(struct spl_image_info *spl_image, * (including SPL content) which is not included in U-Boot image_header. */ if (mhdr->version != 1 || - ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr) || - ( -#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT - mhdr->blockid != IBR_HDR_SPI_ID && -#endif -#ifdef CONFIG_SPL_SATA - mhdr->blockid != IBR_HDR_SATA_ID && -#endif -#ifdef CONFIG_SPL_MMC - mhdr->blockid != IBR_HDR_SDIO_ID && -#endif - 1 - )) { - printf("ERROR: Not valid SPI/NAND/SATA/SDIO kwbimage v1\n"); + ((mhdr->headersz_msb << 16) | mhdr->headersz_lsb) < sizeof(*mhdr)) { + printf("ERROR: Invalid kwbimage v1\n"); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_SPL_SPI_FLASH_SUPPORT) && + bootdev->boot_device == BOOT_DEVICE_SPI && + mhdr->blockid != IBR_HDR_SPI_ID) { + printf("ERROR: Wrong blockid (0x%x) in SPI kwbimage\n", + mhdr->blockid); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_SPL_SATA) && + bootdev->boot_device == BOOT_DEVICE_SATA && + mhdr->blockid != IBR_HDR_SATA_ID) { + printf("ERROR: Wrong blockid (0x%x) in SATA kwbimage\n", + mhdr->blockid); + return -EINVAL; + } + + if (IS_ENABLED(CONFIG_SPL_MMC) && + (bootdev->boot_device == BOOT_DEVICE_MMC1 || + bootdev->boot_device == BOOT_DEVICE_MMC2 || + bootdev->boot_device == BOOT_DEVICE_MMC2_2) && + mhdr->blockid != IBR_HDR_SDIO_ID) { + printf("ERROR: Wrong blockid (0x%x) in SDIO kwbimage\n", + mhdr->blockid); return -EINVAL; } spl_image->offset = mhdr->srcaddr; -#ifdef CONFIG_SPL_SATA /* * For SATA srcaddr is specified in number of sectors. * The main header is must be stored at sector number 1. * This expects that sector size is 512 bytes and recalculates * data offset to bytes relative to the main header. */ - if (mhdr->blockid == IBR_HDR_SATA_ID) { + if (IS_ENABLED(CONFIG_SPL_SATA) && mhdr->blockid == IBR_HDR_SATA_ID) { if (spl_image->offset < 1) { - printf("ERROR: Wrong SATA srcaddr in kwbimage\n"); + printf("ERROR: Wrong srcaddr (0x%08x) in SATA kwbimage\n", + spl_image->offset); return -EINVAL; } spl_image->offset -= 1; spl_image->offset *= 512; } -#endif -#ifdef CONFIG_SPL_MMC /* * For SDIO (eMMC) srcaddr is specified in number of sectors. * This expects that sector size is 512 bytes and recalculates * data offset to bytes. */ - if (mhdr->blockid == IBR_HDR_SDIO_ID) + if (IS_ENABLED(CONFIG_SPL_MMC) && mhdr->blockid == IBR_HDR_SDIO_ID) spl_image->offset *= 512; -#endif + + if (spl_image->offset % 4 != 0) { + printf("ERROR: Wrong srcaddr (0x%08x) in kwbimage\n", + spl_image->offset); + return -EINVAL; + } + + if (mhdr->blocksize <= 4 || mhdr->blocksize % 4 != 0) { + printf("ERROR: Wrong blocksize (0x%08x) in kwbimage\n", + mhdr->blocksize); + return -EINVAL; + } spl_image->size = mhdr->blocksize; spl_image->entry_point = mhdr->execaddr; diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 3499c4c..910e805 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -348,7 +348,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, ret = spl_load_simple_fit(spl_image, &load, load_offset, header); } else { - ret = spl_parse_image_header(spl_image, header); + ret = spl_parse_image_header(spl_image, bootdev, header); if (ret) return ret; diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c index 13ffade..36538e7 100644 --- a/arch/arm/mach-tegra/gpu.c +++ b/arch/arm/mach-tegra/gpu.c @@ -46,11 +46,8 @@ int tegra_gpu_enable_node(void *blob, const char *compat) if (!_configured) return 0; - offset = fdt_node_offset_by_compatible(blob, -1, compat); - while (offset != -FDT_ERR_NOTFOUND) { + fdt_for_each_node_by_compatible(offset, blob, -1, compat) fdt_status_okay(blob, offset); - offset = fdt_node_offset_by_compatible(blob, offset, compat); - } return 0; } diff --git a/arch/mips/mach-octeon/octeon_fdt.c b/arch/mips/mach-octeon/octeon_fdt.c index 9b16104..0ccfe14 100644 --- a/arch/mips/mach-octeon/octeon_fdt.c +++ b/arch/mips/mach-octeon/octeon_fdt.c @@ -424,12 +424,8 @@ void __octeon_fixup_fdt_mac_addr(void) } /* Assign 78XX addresses in the order they appear in the device tree. */ - node = fdt_node_offset_by_compatible(working_fdt, -1, "cavium,octeon-7890-bgx-port"); - while (node != -FDT_ERR_NOTFOUND) { + fdt_for_each_node_by_compatible(node, working_fdt, -1, "cavium,octeon-7890-bgx-port") octeon_set_one_fdt_mac(node, &mac); - node = fdt_node_offset_by_compatible(working_fdt, node, - "cavium,octeon-7890-bgx-port"); - } } #endif @@ -450,11 +446,8 @@ void __octeon_fixup_fdt_uart(void) /* Device trees already have good values for fast simulator * output, real boards need the correct value. */ - node = fdt_node_offset_by_compatible(working_fdt, -1, "cavium,octeon-3860-uart"); - while (node != -FDT_ERR_NOTFOUND) { + fdt_for_each_node_by_compatible(node, working_fdt, -1, "cavium,octeon-3860-uart") fdt_setprop_inplace_cell(working_fdt, node, "clock-frequency", clk); - node = fdt_node_offset_by_compatible(working_fdt, node, "cavium,octeon-3860-uart"); - } } /** diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index e552378..a084002 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -268,15 +268,10 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat, * Count the number of pci nodes. * It's needed later when the interleaved liodn offsets are generated. */ - off = fdt_node_offset_by_compatible(fdt, -1, compat); - while (off != -FDT_ERR_NOTFOUND) { + fdt_for_each_node_by_compatible(off, fdt, -1, compat) pci_cnt++; - off = fdt_node_offset_by_compatible(fdt, off, compat); - } - for (off = fdt_node_offset_by_compatible(fdt, -1, compat); - off != -FDT_ERR_NOTFOUND; - off = fdt_node_offset_by_compatible(fdt, off, compat)) { + fdt_for_each_node_by_compatible(off, fdt, -1, compat) { base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc); if (!base_liodn) { char path[64]; |