Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblazeWIP/27Jan2023

Xilinx chnages for v2023.04-rc1

makefile:
- Add multi_dtb_fit dependency

clk:
- Handle error cases

microblaze:
- Disable falcon mode and cleanup code around

xilinx:
- Enable regular expression matching in board_fit_config_name_match()
- Fix FRU handling for 0xC1 format
- Fix Xilinx legacy format eeprom parsing

zynqmp:
- Some DT updates/cleanups
- Fix IDcode for xck24
- Remove empty mini config files
- Add support for k24

versal:
- Remove empty mini config files

versal_net:
- Setup timer when runs in EL3
- Build u-boot.elf for mini configurations

zynq-gem:
- Add support for new compatible strings
- Remove support for Avnet Ultrazedev SOM
- Handle SGMII with PCS phy

spi:
- Add support for gigadevice parts

misc:
- Remove CONFIG_TARGET_VENUS ifdef
- Add missing headers to remove sparse warnings

25 files changed, 142 insertions, 188 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 44256d9..8e83194 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -340,7 +340,6 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
 	zynq-zybo-z7.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	avnet-ultra96-rev1.dtb			\
-	avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb	\
 	zynqmp-a2197-revA.dtb			\
 	zynqmp-dlc21-revA.dtb			\
 	zynqmp-e-a2197-00-revA.dtb		\
@@ -354,6 +353,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-mini-emmc1.dtb			\
 	zynqmp-mini-nand.dtb			\
 	zynqmp-mini-qspi.dtb			\
+	zynqmp-sm-k24-revA.dtb			\
+	zynqmp-smk-k24-revA.dtb			\
 	zynqmp-sm-k26-revA.dtb			\
 	zynqmp-smk-k26-revA.dtb			\
 	zynqmp-sck-kr-g-revA.dtbo		\
diff --git a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts b/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
deleted file mode 100644
index 6d1448e..0000000
--- a/arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-
-/*
- * UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
- * http://ultrazed.org/product/ultrazed-ev-carrier-card
- */
-
-/dts-v1/;
-
-#include "avnet-ultrazedev-som-v1.0.dtsi"
-
-/ {
-	model = "Avnet UltraZed EV Carrier Card v1.0";
-	compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
-		     "xlnx,zynqmp";
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-	aliases {
-		ethernet0 = &gem3;
-		nvmem0 = &eeprom;
-		serial0 = &uart0;
-	};
-};
-
-&uart0 {
-	device_type = "serial";
-	status = "okay";
-};
-
-&i2c_cc {
-	/* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
-	eeprom: eeprom@51 {
-		compatible = "atmel,24c02";
-		reg = <0x51>;
-	};
-
-	/* IDT Versa Clock 5P49V5935B */
-	vc5: clock-generator@6a {
-		compatible = "idt,5p49v5935";
-		reg = <0x6a>;
-		#clock-cells = <1>;
-	};
-};
-
-/* Ethernet RJ-45 */
-&gem3 {
-	status = "okay";
-};
-
-/* microSD card slot */
-&sdhci1 {
-	status = "okay";
-	xlnx,mio-bank = <1>;
-	clock-frequency = <199998000>;
-	max-frequency = <50000000>;
-	no-1-8-v;
-	disable-wp;
-};
diff --git a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi b/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
deleted file mode 100644
index cbcb290..0000000
--- a/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-
-/*
- * UltraZed-EV SoM v1
- * http://ultrazed.org/product/ultrazed-ev
- */
-
-/dts-v1/;
-
-#include "zynqmp.dtsi"
-#include "zynqmp-clk-ccf.dtsi"
-
-/ {
-	model = "Avnet UltraZed EV SoM v1.0";
-	compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
-	memory {
-		device_type = "memory";
-		reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
-		      <0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
-	};
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	status = "okay";
-
-	i2cswitch@70 {
-		compatible = "nxp,pca9543";
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x70>;
-
-		/* I2C connected to Carrier Card via JX3A1/JX3C1 */
-		i2c_cc: i2c@0 {
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-	};
-};
-
-/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
-&gem3 {
-	phy-mode = "rgmii-id";
-	phy-handle = <&gem3phy>;
-	gem3phy: ethernet-phy@0 {
-		reg = <0>;
-	};
-};
-
-/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
-&sdhci0 {
-	status = "okay";
-	xlnx,mio-bank = <0>;
-	clock-frequency = <199998000>;
-};
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts
index 0461219..bf0d89a 100644
--- a/arch/arm/dts/zynqmp-dlc21-revA.dts
+++ b/arch/arm/dts/zynqmp-dlc21-revA.dts
@@ -154,8 +154,6 @@
 
 &usb0 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_0 {
@@ -170,8 +168,6 @@
 
 &usb1 {
 	status = "disabled"; /* Any unknown issue with USB-C */
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
index e004283..02d2427 100644
--- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts
@@ -303,8 +303,6 @@
 
 &usb0 { /* USB0 MIO52-63 */
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_0 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 1fa023f..2d7fe59 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -461,8 +461,6 @@
 
 &usb0 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_0 {
@@ -474,8 +472,6 @@
 
 &usb1 {
 	status = "disabled"; /* not at mem board */
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 2271a6a..e46748d 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -463,8 +463,6 @@
 
 &usb0 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_0 {
@@ -476,8 +474,6 @@
 
 &usb1 {
 	status = "disabled"; /* not at mem board */
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index a89046a..f564817 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -457,8 +457,6 @@
 
 &usb0 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_0 {
@@ -470,8 +468,6 @@
 
 &usb1 {
 	status = "disabled"; /* not at mem board */
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index b3fe42f..d63deb8 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -543,8 +543,6 @@
 
 &usb0 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 	phy-names = "usb3-phy";
 	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
 };
@@ -559,8 +557,6 @@
 
 &usb1 {
 	status = "okay";
-	xlnx,usb-polarity = <0>;
-	xlnx,usb-reset-mode = <0>;
 };
 
 &dwc3_1 {
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 735c1e3..83c6502 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -18,6 +18,7 @@
 &{/} {
 	compatible = "xlnx,zynqmp-sk-kr260-revA",
 		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+	model = "ZynqMP KR260 revA";
 
 	ina260-u14 {
 		compatible = "iio-hwmon";
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 6359061..f41a2f8 100644
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -18,6 +18,7 @@
 &{/} {
 	compatible = "xlnx,zynqmp-sk-kr260-revB",
 		     "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+	model = "ZynqMP KR260 revB";
 
 	ina260-u14 {
 		compatible = "iio-hwmon";
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index b714bd3..0be5b29 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -25,6 +25,7 @@
 		     "xlnx,zynqmp-sk-kv260-revY",
 		     "xlnx,zynqmp-sk-kv260-revZ",
 		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+	model = "ZynqMP KV260 revA";
 };
 
 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index a1d8f9f..fca57a6 100644
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -19,6 +19,7 @@
 	compatible = "xlnx,zynqmp-sk-kv260-rev1",
 		     "xlnx,zynqmp-sk-kv260-revB",
 		     "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+	model = "ZynqMP KV260 revB";
 };
 
 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts
new file mode 100644
index 0000000..2451440
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SM-K24 RevA
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+	model = "ZynqMP SM-K24 RevA";
+	compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24",
+		     "xlnx,zynqmp";
+
+	memory@0 {
+		device_type = "memory"; /* 2GB */
+		reg = <0 0 0 0x80000000>;
+	};
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index bae24aa..aafaaec 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -53,7 +53,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
-		fwuen {
+		key-fwuen {
 			label = "fwuen";
 			gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
 			linux,code = <BTN_MISC>;
diff --git a/arch/arm/dts/zynqmp-smk-k24-revA.dts b/arch/arm/dts/zynqmp-smk-k24-revA.dts
new file mode 100644
index 0000000..7308983
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k24-revA.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K24 RevA
+ *
+ * (C) Copyright 2020 - 2021, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+#include "zynqmp-sm-k24-revA.dts"
+
+/ {
+	model = "ZynqMP SMK-K24 RevA";
+	compatible = "xlnx,zynqmp-smk-k24-revA", "xlnx,zynqmp-smk-k24",
+		     "xlnx,zynqmp";
+};
+
+&sdhci0 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index 5e7bc73..eea703a 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -49,7 +49,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
-		sw4 {
+		switch-4 {
 			label = "sw4";
 			gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
 			linux,code = <KEY_POWER>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9d8e551..d78bfb8 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -47,7 +47,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
-		sw19 {
+		switch-19 {
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 2422558..de3b5ab 100644
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -16,16 +16,20 @@
 
 &gem3 {
 	phy-handle = <&phyc>;
-	phyc: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
-		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+	mdio: mdio {
+		phyc: ethernet-phy@c {
+			#phy-cells = <0x1>;
+			compatible = "ethernet-phy-id2000.a231";
+			reg = <0xc>;
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
+		/* Cleanup from RevA */
+		/delete-node/ ethernet-phy@21;
 	};
-	/* Cleanup from RevA */
-	/delete-node/ ethernet-phy@21;
 };
 
 /* Fix collision with u61 */
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 4858b4d..266c24e 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -47,7 +47,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
-		sw19 {
+		switch-19 {
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 2e95f22..8535cc0 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -47,7 +47,7 @@
 	gpio-keys {
 		compatible = "gpio-keys";
 		autorepeat;
-		sw19 {
+		switch-19 {
 			label = "sw19";
 			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
 			linux,code = <KEY_DOWN>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b210bc4..0a06c73 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -280,10 +280,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 124 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14e8>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan2: dma-controller@fd510000 {
@@ -293,10 +293,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 125 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14e9>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan3: dma-controller@fd520000 {
@@ -306,10 +306,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 126 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14ea>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan4: dma-controller@fd530000 {
@@ -319,10 +319,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 127 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14eb>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan5: dma-controller@fd540000 {
@@ -332,10 +332,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 128 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14ec>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan6: dma-controller@fd550000 {
@@ -345,10 +345,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 129 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14ed>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan7: dma-controller@fd560000 {
@@ -358,10 +358,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 130 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14ee>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		fpd_dma_chan8: dma-controller@fd570000 {
@@ -371,10 +371,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 131 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <128>;
 			iommus = <&smmu 0x14ef>;
 			power-domains = <&zynqmp_firmware PD_GDMA>;
-			#dma-cells = <1>;
 		};
 
 		gic: interrupt-controller@f9010000 {
@@ -411,10 +411,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 77 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x868>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan2: dma-controller@ffa90000 {
@@ -424,10 +424,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 78 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x869>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan3: dma-controller@ffaa0000 {
@@ -437,10 +437,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 79 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86a>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan4: dma-controller@ffab0000 {
@@ -450,10 +450,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 80 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86b>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan5: dma-controller@ffac0000 {
@@ -463,10 +463,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 81 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86c>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan6: dma-controller@ffad0000 {
@@ -476,10 +476,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 82 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86d>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan7: dma-controller@ffae0000 {
@@ -489,10 +489,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 83 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86e>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		lpd_dma_chan8: dma-controller@ffaf0000 {
@@ -502,10 +502,10 @@
 			interrupt-parent = <&gic>;
 			interrupts = <0 84 4>;
 			clock-names = "clk_main", "clk_apb";
+			#dma-cells = <1>;
 			xlnx,bus-width = <64>;
 			iommus = <&smmu 0x86f>;
 			power-domains = <&zynqmp_firmware PD_ADMA>;
-			#dma-cells = <1>;
 		};
 
 		mc: memory-controller@fd070000 {
@@ -540,6 +540,7 @@
 			iommus = <&smmu 0x874>;
 			power-domains = <&zynqmp_firmware PD_ETH_0>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
+			reset-names = "gem0_rst";
 		};
 
 		gem1: ethernet@ff0c0000 {
@@ -554,6 +555,7 @@
 			iommus = <&smmu 0x875>;
 			power-domains = <&zynqmp_firmware PD_ETH_1>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+			reset-names = "gem1_rst";
 		};
 
 		gem2: ethernet@ff0d0000 {
@@ -568,6 +570,7 @@
 			iommus = <&smmu 0x876>;
 			power-domains = <&zynqmp_firmware PD_ETH_2>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
+			reset-names = "gem2_rst";
 		};
 
 		gem3: ethernet@ff0e0000 {
@@ -582,6 +585,7 @@
 			iommus = <&smmu 0x877>;
 			power-domains = <&zynqmp_firmware PD_ETH_3>;
 			resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
+			reset-names = "gem3_rst";
 		};
 
 		gpio: gpio@ff0a0000 {
@@ -842,7 +846,7 @@
 			power-domains = <&zynqmp_firmware PD_UART_1>;
 		};
 
-		usb0: usb0@ff9d0000 {
+		usb0: usb@ff9d0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
@@ -866,7 +870,6 @@
 				interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
 				iommus = <&smmu 0x860>;
 				snps,quirk-frame-length-adjustment = <0x20>;
-				snps,refclk_fladj;
 				clock-names = "ref";
 				snps,enable_guctl1_resume_quirk;
 				snps,enable_guctl1_ipd_quirk;
@@ -875,7 +878,7 @@
 			};
 		};
 
-		usb1: usb1@ff9e0000 {
+		usb1: usb@ff9e0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
@@ -898,7 +901,6 @@
 				interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
 				iommus = <&smmu 0x861>;
 				snps,quirk-frame-length-adjustment = <0x20>;
-				snps,refclk_fladj;
 				clock-names = "ref";
 				snps,enable_guctl1_resume_quirk;
 				snps,enable_guctl1_ipd_quirk;
@@ -934,21 +936,23 @@
 			interrupt-names = "ams-irq";
 			reg = <0x0 0xffa50000 0x0 0x800>;
 			reg-names = "ams-base";
-			#address-cells = <2>;
-			#size-cells = <2>;
+			#address-cells = <1>;
+			#size-cells = <1>;
 			#io-channel-cells = <1>;
-			ranges;
+			ranges = <0 0 0xffa50800 0x800>;
 
-			ams_ps: ams_ps@ffa50800 {
+			ams_ps: ams_ps@0 {
 				compatible = "xlnx,zynqmp-ams-ps";
 				status = "disabled";
-				reg = <0x0 0xffa50800 0x0 0x400>;
+				reg = <0x0 0x400>;
 			};
 
-			ams_pl: ams_pl@ffa50c00 {
+			ams_pl: ams_pl@400 {
 				compatible = "xlnx,zynqmp-ams-pl";
 				status = "disabled";
-				reg = <0x0 0xffa50c00 0x0 0x400>;
+				reg = <0x400 0x400>;
+				#address-cells = <1>;
+				#size-cells = <0>;
 			};
 		};
 
diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig
index 62825e1..edff5b0 100644
--- a/arch/arm/mach-versal-net/Kconfig
+++ b/arch/arm/mach-versal-net/Kconfig
@@ -21,6 +21,18 @@ config SYS_CONFIG_NAME
 	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
 	  will be used for board configuration.
 
+config COUNTER_FREQUENCY
+	int "Timer clock frequency"
+	default 0
+	help
+	  Setup time clock frequency for certain platform
+
+config IOU_SWITCH_DIVISOR0
+	hex "IOU switch divisor0"
+	default 0x20
+	help
+	  Setup time clock divisor for input clock.
+
 config SYS_MEM_RSVD_FOR_MMU
 	bool "Reserve memory for MMU Table"
 	help
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index 808ce48..c5e4e22 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -8,6 +8,36 @@
 #include <linux/bitops.h>
 #endif
 
+struct crlapb_regs {
+	u32 reserved0[67];
+	u32 cpu_r5_ctrl;
+	u32 reserved;
+	u32 iou_switch_ctrl; /* 0x114 */
+	u32 reserved1[13];
+	u32 timestamp_ref_ctrl; /* 0x14c */
+	u32 reserved3[108];
+	u32 rst_cpu_r5;
+	u32 reserved2[17];
+	u32 rst_timestamp; /* 0x348 */
+};
+
+struct iou_scntrs_regs {
+	u32 counter_control_register; /* 0x0 */
+	u32 reserved0[7];
+	u32 base_frequency_id_register; /* 0x20 */
+};
+
+#define VERSAL_NET_CRL_APB_BASEADDR		0xEB5E0000
+#define VERSAL_NET_IOU_SCNTR_SECURE		0xEC920000
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT	BIT(25)
+#define IOU_SWITCH_CTRL_CLKACT_BIT		BIT(25)
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT		8
+#define IOU_SCNTRS_CONTROL_EN			1
+
+#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE)
+
 #define PMC_TAP	0xF11A0000
 
 #define PMC_TAP_IDCODE		(PMC_TAP + 0)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index cea6d56..eaa095b 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -14,8 +14,6 @@
 #include <asm/u-boot.h>
 #include <linux/stringify.h>
 
-bool boot_linux;
-
 void board_boot_order(u32 *spl_boot_list)
 {
 	spl_boot_list[0] = BOOT_DEVICE_NOR;
@@ -41,17 +39,12 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
 
 	image_entry(NULL, 0, (ulong)spl_image->arg);
 }
-#endif /* CONFIG_SPL_OS_BOOT */
 
 int spl_start_uboot(void)
 {
-#ifdef CONFIG_SPL_OS_BOOT
-	if (boot_linux)
-		return 0;
-#endif
-
-	return 1;
+	return 0;
 }
+#endif /* CONFIG_SPL_OS_BOOT */
 
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {