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| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-12-02 00:19:14 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-12-02 00:27:42 +0100 |
| commit | 4fc495e9e2e497afee383294a6ee9212e9a8bd73 (patch) | |
| tree | c093c150990b48a03d950bb533cf008f404be761 /arch | |
| parent | cd401abcd532c59cdaaf6ffeed762386c1813e58 (diff) | |
| download | u-boot-4fc495e9e2e497afee383294a6ee9212e9a8bd73.zip u-boot-4fc495e9e2e497afee383294a6ee9212e9a8bd73.tar.gz u-boot-4fc495e9e2e497afee383294a6ee9212e9a8bd73.tar.bz2 | |
rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK
The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.
Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3128.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h index 3d8317e..90012c7 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h @@ -187,7 +187,7 @@ enum { DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, DCLK_VOP_PLL_SEL_CPLL = 0, DCLK_VOP_DIV_CON_SHIFT = 8, - DCLK_VOP_DIV_CON_MASK = 0xfff << DCLK_VOP_DIV_CON_SHIFT, + DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT, /* CRU_CLKSEL31_CON */ VIO0_PLL_SHIFT = 5, |