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| author | Dinesh Maniyam <dinesh.maniyam@intel.com> | 2022-05-31 16:05:56 +0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2022-06-17 16:27:04 +0800 |
| commit | 7f8533078291bc1c96125ec0619ffd5d01ecc83d (patch) | |
| tree | c52ded8226c2612f32227dbb663f244001e88c39 /arch | |
| parent | 373c1428a0374c29f19cca76f12c0e93378a634a (diff) | |
| download | u-boot-7f8533078291bc1c96125ec0619ffd5d01ecc83d.zip u-boot-7f8533078291bc1c96125ec0619ffd5d01ecc83d.tar.gz u-boot-7f8533078291bc1c96125ec0619ffd5d01ecc83d.tar.bz2 | |
arm: dts: socfpga: agilex: Add freeze controller node
The freeze controller is required for FPGA partial reconfig.
This node is disable on default.
Enable this node via u-boot fdt command when needed.
Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com>
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6cac36a..2400fad 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_agilex-u-boot.dtsi" @@ -11,6 +11,15 @@ aliases { spi0 = &qspi; i2c0 = &i2c1; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; memory { |