diff options
author | Tom Rini <trini@konsulko.com> | 2016-07-12 08:15:17 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-07-12 08:15:17 -0400 |
commit | b8e599746cac1833328bc3a8e37eeefe346baf90 (patch) | |
tree | ec49cc9ac3c8638fe11774e945cf0bcc4e87c1f4 /arch | |
parent | bff97dde8c8cf6fd5f04bb26fca83f61eadc1741 (diff) | |
parent | 9532fe3b40ddf66ef976dee3d5cf1d8b3396bf4d (diff) | |
download | u-boot-b8e599746cac1833328bc3a8e37eeefe346baf90.zip u-boot-b8e599746cac1833328bc3a8e37eeefe346baf90.tar.gz u-boot-b8e599746cac1833328bc3a8e37eeefe346baf90.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-x86
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/Kconfig | 4 | ||||
-rw-r--r-- | arch/x86/cpu/baytrail/Kconfig | 11 | ||||
-rw-r--r-- | arch/x86/cpu/baytrail/acpi.c | 26 | ||||
-rw-r--r-- | arch/x86/cpu/ivybridge/sdram.c | 5 | ||||
-rw-r--r-- | arch/x86/cpu/quark/acpi.c | 7 | ||||
-rw-r--r-- | arch/x86/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/x86/dts/baytrail_som-db5800-som-6867.dts | 289 | ||||
-rw-r--r-- | arch/x86/include/asm/acpi/global_nvs.h | 19 | ||||
-rw-r--r-- | arch/x86/include/asm/acpi_table.h | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl | 15 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 19 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-baytrail/acpi/platform.asl | 3 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-baytrail/global_nvs.h | 21 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-quark/acpi/global_nvs.asl | 14 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-quark/acpi/platform.asl | 3 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-quark/global_nvs.h | 20 | ||||
-rw-r--r-- | arch/x86/lib/acpi_table.c | 22 | ||||
-rw-r--r-- | arch/x86/lib/fsp/fsp_support.c | 2 |
18 files changed, 474 insertions, 13 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d2307..29d1120 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -8,6 +8,9 @@ choice prompt "Mainboard vendor" default VENDOR_EMULATION +config VENDOR_ADVANTECH + bool "advantech" + config VENDOR_CONGATEC bool "congatec" @@ -29,6 +32,7 @@ config VENDOR_INTEL endchoice # board-specific options below +source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" source "board/efi/Kconfig" diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 407feb2..1c8ac37 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -7,3 +7,14 @@ config INTEL_BAYTRAIL bool select HAVE_FSP if !EFI + +if INTEL_BAYTRAIL +config INTERNAL_UART + bool "Enable the SoC integrated legacy UART" + help + There is a legacy UART integrated into the Bay Trail SoC. + A maximum baud rate of 115200 bps is supported. For this + reason, it is recommended that the UART port be used for + debug purposes only, eg: U-Boot console. + +endif diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 5ee4868..fa92d88 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -5,10 +5,14 @@ */ #include <common.h> +#include <cpu.h> +#include <dm.h> +#include <dm/uclass-internal.h> #include <asm/acpi_table.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +165,25 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; +} diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 9d9f63d..e0b06b5 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -458,6 +458,11 @@ int dram_init(void) struct udevice *dev, *me_dev; int ret; + /* We need the pinctrl set up early */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); + if (ret) + return ret; + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 8f69829..3968f7a 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -9,6 +9,7 @@ #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +162,9 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + /* quark is a uni-processor */ + gnvs->pcnt = 1; +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 23156bb..4f07f41 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ - broadwell_som-6896.dtb + broadwell_som-6896.dtb \ + baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts new file mode 100644 index 0000000..64e2e52 --- /dev/null +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Advantech SOM-DB5800-SOM-6867"; + compatible = "advantech,som-db5800-som-6867", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* HDA_RSTB */ + soc_gpio_s0_8@0 { + pad-offset = <0x220>; + mode-func = <2>; + }; + + /* HDA_SYNC */ + soc_gpio_s0_9@0 { + pad-offset = <0x250>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_CLK */ + soc_gpio_s0_10@0 { + pad-offset = <0x240>; + mode-func = <2>; + }; + + /* HDA_SDO */ + soc_gpio_s0_11@0 { + pad-offset = <0x260>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_SDI0 */ + soc_gpio_s0_12@0 { + pad-offset = <0x270>; + mode-func = <2>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "macronix,mx25l6405d", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-azalia; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,enable-igd; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; + +}; diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h new file mode 100644 index 0000000..7f2ffd4 --- /dev/null +++ b/arch/x86/include/asm/acpi/global_nvs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ACPI_GNVS_H_ +#define _ACPI_GNVS_H_ + +/* + * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and + * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file + * to declare the GNVS OperationRegion, as well as write_acpi_tables() + * for the GNVS address runtime fix up. + */ +#define ACPI_GNVS_ADDR 0xdeadbeef +#define ACPI_GNVS_SIZE 0x100 + +#endif /* _ACPI_GNVS_H_ */ diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 56aa282..caff4d8 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -299,6 +299,9 @@ struct acpi_mcfg_mmconfig { /* PM1_CNT bit defines */ #define PM1_CNT_SCI_EN (1 << 0) +/* ACPI global NVS structure */ +struct acpi_global_nvs; + /* These can be used by the target port */ void acpi_fill_header(struct acpi_table_header *header, char *signature); @@ -312,4 +315,5 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); +void acpi_create_gnvs(struct acpi_global_nvs *gnvs); u32 write_acpi_tables(u32 start); diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl new file mode 100644 index 0000000..a28d4df --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl index 22f0d68..fe34d32 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -119,17 +119,14 @@ Device (LPCB) Method(_STA, 0, Serialized) { - /* - * TODO: - * - * Need to hide the internal UART depending on whether - * internal UART is enabled or not so that external - * SuperIO UART can be exposed to system. - */ - Store(1, UI3E) - Store(1, UI4E) - Store(1, C1EN) - Return (STA_VISIBLE) + If (LEqual(IURE, 1)) { + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + } Else { + Return (STA_MISSING) + } } diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index 6bc82ec..a80d2c0 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h new file mode 100644 index 0000000..56e3626 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl new file mode 100644 index 0000000..6f0435e --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ +} diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl index bd72842..1ecf153 100644 --- a/arch/x86/include/asm/arch-quark/acpi/platform.asl +++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) diff --git a/arch/x86/include/asm/arch-quark/global_nvs.h b/arch/x86/include/asm/arch-quark/global_nvs.h new file mode 100644 index 0000000..0231da0 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/global_nvs.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[255]; +}; + +#endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index bb71286..7001e8b 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -11,10 +11,12 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <asm/acpi/global_nvs.h> #include <asm/acpi_table.h> #include <asm/io.h> #include <asm/lapic.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> /* * IASL compiles the dsdt entries and writes the hex values @@ -336,6 +338,7 @@ u32 write_acpi_tables(u32 start) struct acpi_fadt *fadt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; + int i; current = start; @@ -383,6 +386,25 @@ u32 write_acpi_tables(u32 start) current += dsdt->length - sizeof(struct acpi_table_header); current = ALIGN(current, 16); + /* Pack GNVS into the ACPI table area */ + for (i = 0; i < dsdt->length; i++) { + u32 *gnvs = (u32 *)((u32)dsdt + i); + if (*gnvs == ACPI_GNVS_ADDR) { + debug("Fix up global NVS in DSDT to 0x%08x\n", current); + *gnvs = current; + break; + } + } + + /* Update DSDT checksum since we patched the GNVS address */ + dsdt->checksum = 0; + dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); + + /* Fill in platform-specific global NVS variables */ + acpi_create_gnvs((struct acpi_global_nvs *)current); + current += sizeof(struct acpi_global_nvs); + current = ALIGN(current, 16); + debug("ACPI: * FADT\n"); fadt = (struct acpi_fadt *)current; current += sizeof(struct acpi_fadt); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index b05dced..a480361 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -110,7 +110,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct upd_region *fsp_upd; #endif -#ifdef CONFIG_DEBUG_UART +#ifdef CONFIG_INTERNAL_UART setup_internal_uart(1); #endif |