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| author | Tom Rini <trini@konsulko.com> | 2019-10-14 21:00:10 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-10-14 21:00:10 -0400 |
| commit | 6891152a4596d38ac25d2fe1238e3b6a938554b8 (patch) | |
| tree | 306fd58a952c88cb9116285c91cf8ed3dd19b5c3 /arch | |
| parent | 6f1f28b8e19a0d48b930a577fd8c8579cb66079b (diff) | |
| parent | e6281b8ab07e0d64be3f5f829d5a3d3a08390daa (diff) | |
| download | u-boot-6891152a4596d38ac25d2fe1238e3b6a938554b8.zip u-boot-6891152a4596d38ac25d2fe1238e3b6a938554b8.tar.gz u-boot-6891152a4596d38ac25d2fe1238e3b6a938554b8.tar.bz2 | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- vining_fpga updates
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_vining_fpga.dts | 17 | ||||
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 10 |
3 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index db55a4e..44bedd8 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -20,7 +20,7 @@ }; &mmc { - u-boot,dm-pre-reloc; + status = "disabled"; }; &qspi { diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts index ac57f41..3fb6e14 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR X11) /* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * Copyright (C) 2015-2019 Marek Vasut <marex@denx.de> */ #include "socfpga_cyclone5.dtsi" @@ -8,7 +8,7 @@ #include <dt-bindings/input/input.h> / { - model = "samtec VIN|ING FPGA"; + model = "Softing VIN|ING FPGA"; compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga"; chosen { @@ -65,6 +65,11 @@ }; }; +&gmac0 { + status = "disabled"; + phy-mode = "gmii"; +}; + &gmac1 { status = "okay"; phy-mode = "rgmii"; @@ -84,10 +89,14 @@ rxd1-skew-ps = <0>; rxd2-skew-ps = <0>; rxd3-skew-ps = <0>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; txen-skew-ps = <0>; - txc-skew-ps = <1560>; + txc-skew-ps = <1860>; rxdv-skew-ps = <0>; - rxc-skew-ps = <1200>; + rxc-skew-ps = <1860>; }; }; }; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 45de153..fc0a542 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -100,8 +100,8 @@ config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 -config TARGET_SOCFPGA_SAMTEC_VINING_FPGA - bool "samtec VIN|ING FPGA (Cyclone V)" +config TARGET_SOCFPGA_SOFTING_VINING_FPGA + bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT select TARGET_SOCFPGA_CYCLONE5 @@ -145,7 +145,7 @@ config SYS_BOARD default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -155,7 +155,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES - default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO @@ -178,6 +178,6 @@ config SYS_CONFIG_NAME default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK - default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA + default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA endif |