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| author | Suresh Gupta <suresh.gupta@nxp.com> | 2017-08-29 19:12:43 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 08:00:13 -0700 |
| commit | 22c51855bf79b4ef767f35067472d337858423b3 (patch) | |
| tree | 0a502de971aaee88ae848c4d13a0cc5c178ed7f3 /arch | |
| parent | 5436c6a347918bf278d4cc9e5678f9bd94bdbcbc (diff) | |
| download | u-boot-22c51855bf79b4ef767f35067472d337858423b3.zip u-boot-22c51855bf79b4ef767f35067472d337858423b3.tar.gz u-boot-22c51855bf79b4ef767f35067472d337858423b3.tar.bz2 | |
armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC
For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index c4e5ecc..3d564d6 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -199,7 +199,8 @@ static struct mm_region final_map[] = { }, { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, - PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, @@ -208,7 +209,8 @@ static struct mm_region final_map[] = { }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, - PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, |