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| author | Samuel Holland <samuel@sholland.org> | 2021-04-18 22:21:41 -0500 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-08-01 00:11:34 +0100 |
| commit | 1ebfc0c631e3073d6f7ae97aa001b26b660c08c4 (patch) | |
| tree | d3052755235d40eb4ca41dbdf40e0eea431ce430 /arch | |
| parent | 1011ebc72bda061cc9d34c1d6ff4506291a88657 (diff) | |
| download | u-boot-1ebfc0c631e3073d6f7ae97aa001b26b660c08c4.zip u-boot-1ebfc0c631e3073d6f7ae97aa001b26b660c08c4.tar.gz u-boot-1ebfc0c631e3073d6f7ae97aa001b26b660c08c4.tar.bz2 | |
sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.
Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 02ce739..d4c795d 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -11,7 +11,18 @@ #define SUNXI_SRAM_A1_BASE 0x00000000 #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ +#if defined(CONFIG_SUNXI_GEN_SUN6I) && \ + !defined(CONFIG_MACH_SUN8I_R40) && \ + !defined(CONFIG_MACH_SUN8I_V3S) +#define SUNXI_SRAM_A2_BASE 0x00040000 +#ifdef CONFIG_MACH_SUN8I_H3 +#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */ +#else +#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */ +#endif +#else #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#endif #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ |