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authorSuman Anna <s-anna@ti.com>2021-07-26 16:13:07 -0500
committerLokesh Vutla <lokeshvutla@ti.com>2021-07-27 11:00:44 +0530
commit05e858aefe8da523b25080ad9034a9322f7a1d20 (patch)
tree36e0e68993b42cbde029f539cd0a89a65c7c4e7e /arch
parent31b3d7a01851552ca1b4e962db5922db66d3b883 (diff)
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arm: mach-k3: j721e: Move booting of Main R5FSS Core0 to A72 U-Boot
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL itself to achieve certain product-level early-boot metrics. This is no longer supported after the R5 SPL re-architecture (support merged for v2021.10-rc1). Move the booting of this core altogether from R5 SPL to A72 U-Boot. The env variables are left as is for now, and will be cleaned up in a subsequent patch. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-k3/j721e_init.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index e9e076c..55d7383 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -377,7 +377,11 @@ void start_non_linux_remote_cores(void)
int size = 0, ret;
u32 loadaddr = 0;
- if (!soc_is_j721e())
+ /*
+ * Skip booting of Main R5FSS Core0 in R5 SPL. This is no longer
+ * supported after the R5 SPL re-architecture.
+ */
+ if (soc_is_j721e() || soc_is_j7200())
return;
size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",