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| author | Harini Katakam <harini.katakam@amd.com> | 2023-07-10 14:37:33 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-07-21 09:00:39 +0200 |
| commit | 6a251f24888b1ae3a1d20e21b5886e9cbd0e289b (patch) | |
| tree | 85d2561641f5e7db3b5bf2a21a3ec93dd8bd6de0 /arch | |
| parent | 414fc91f4ecbcd00a7d23e33baf39a0e2f6bac96 (diff) | |
| download | u-boot-6a251f24888b1ae3a1d20e21b5886e9cbd0e289b.zip u-boot-6a251f24888b1ae3a1d20e21b5886e9cbd0e289b.tar.gz u-boot-6a251f24888b1ae3a1d20e21b5886e9cbd0e289b.tar.bz2 | |
arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 8229244..a81b3f6 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -165,6 +165,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 96a5121..0ac2086 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -152,6 +152,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; |