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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2018-04-25 16:28:44 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-05-09 09:17:51 -0500 |
| commit | 945fad57be827482091c6d39443d51052c7a8d7d (patch) | |
| tree | a81b3ef7bf38054f9e3c1008cc60d9603492a036 /arch | |
| parent | 8044900a5b97079396049d7e0d1d15b042a0e19a (diff) | |
| download | u-boot-945fad57be827482091c6d39443d51052c7a8d7d.zip u-boot-945fad57be827482091c6d39443d51052c7a8d7d.tar.gz u-boot-945fad57be827482091c6d39443d51052c7a8d7d.tar.bz2 | |
armv8/fsl-lsch2: correct QMAN clock
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 7edc06d..546de33 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -469,6 +469,14 @@ config SYS_FSL_SDHC_CLK_DIV help This is the divider that is used to derive SDHC clock from Platform clock, in another word SDHC_clk = Platform_clk / this_divider. + +config SYS_FSL_QMAN_CLK_DIV + int "QMAN clock divider" + default 1 if ARCH_LS1043A + default 2 + help + This is the divider that is used to derive QMAN clock from Platform + clock, in another word QMAN_clk = Platform_clk / this_divider. endmenu config RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 8386678..723d7ea 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -155,7 +155,9 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sys_info->freq_qman = sys_info->freq_systembus; + sys_info->freq_qman = (sys_info->freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_QMAN_CLK_DIV; #endif } |