diff options
| author | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-20 08:09:24 -0400 |
| commit | 2f7821a9278e710b2e825018303c2942f920a77d (patch) | |
| tree | 8e4d97bcd17960370457134c0770276e5fecc209 /arch | |
| parent | a9e90d357bbf539e07c1d971161e027eb335183e (diff) | |
| parent | eae488b77906692627622abc61f5b7160b6eb2a4 (diff) | |
| download | u-boot-2f7821a9278e710b2e825018303c2942f920a77d.zip u-boot-2f7821a9278e710b2e825018303c2942f920a77d.tar.gz u-boot-2f7821a9278e710b2e825018303c2942f920a77d.tar.bz2 | |
Merge tag 'u-boot-stm32-20220620' of https://source.denx.de/u-boot/custodians/u-boot-stm into next
- Add STM32MP13 SoCs support with associated board STM32M135F-DK
- Correct livetree support in stm32mp1 boards
- Activate livetree for stm32mp15 DHSOM boards
Diffstat (limited to 'arch')
25 files changed, 1792 insertions, 536 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2f8c793..c618aad 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1928,7 +1928,7 @@ config ARCH_STM32 imply CMD_DM config ARCH_STI - bool "Support STMicrolectronics SoCs" + bool "Support STMicroelectronics SoCs" select BLK select CPU_V7A select DM @@ -1956,7 +1956,6 @@ config ARCH_STM32MP select OF_SYSTEM_SETUP select PINCTRL select REGMAP - select SUPPORT_SPL select SYSCON select SYSRESET select SYS_THUMB_BUILD diff --git a/arch/arm/cpu/armv7/stv0991/lowlevel.S b/arch/arm/cpu/armv7/stv0991/lowlevel.S index 218ac70..5733eaa1 100644 --- a/arch/arm/cpu/armv7/stv0991/lowlevel.S +++ b/arch/arm/cpu/armv7/stv0991/lowlevel.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * (C) Copyright 2014 stmicroelectronics + * (C) Copyright 2014 STMicroelectronics */ #include <config.h> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f78f668..cae0085 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1162,6 +1162,9 @@ dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb +dtb-$(CONFIG_STM32MP13x) += \ + stm32mp135f-dk.dtb + dtb-$(CONFIG_STM32MP15x) += \ stm32mp157a-dk1.dtb \ stm32mp157a-icore-stm32mp1-ctouch2.dtb \ diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi new file mode 100644 index 0000000..d2472cd --- /dev/null +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { + pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ + <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ + <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ + <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ + <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ + <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ + <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + uart4_pins_a: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi new file mode 100644 index 0000000..1b5b358 --- /dev/null +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + pinctrl0 = &pinctrl; + }; + + /* need PSCI for sysreset during board_f */ + psci { + u-boot,dm-pre-proper; + }; + + soc { + u-boot,dm-pre-reloc; + + ddr: ddr@5a003000 { + u-boot,dm-pre-reloc; + + compatible = "st,stm32mp13-ddr"; + + reg = <0x5A003000 0x550 + 0x5A004000 0x234>; + + status = "okay"; + }; + }; +}; + +&bsec { + u-boot,dm-pre-reloc; +}; + +&gpioa { + u-boot,dm-pre-reloc; +}; + +&gpiob { + u-boot,dm-pre-reloc; +}; + +&gpioc { + u-boot,dm-pre-reloc; +}; + +&gpiod { + u-boot,dm-pre-reloc; +}; + +&gpioe { + u-boot,dm-pre-reloc; +}; + +&gpiof { + u-boot,dm-pre-reloc; +}; + +&gpiog { + u-boot,dm-pre-reloc; +}; + +&gpioh { + u-boot,dm-pre-reloc; +}; + +&gpioi { + u-boot,dm-pre-reloc; +}; + +&iwdg2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi new file mode 100644 index 0000000..950e172 --- /dev/null +++ b/arch/arm/dts/stm32mp131.dtsi @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + clocks { + clk_axi: clk-axi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <266500000>; + }; + + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: clk-hsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lsi: clk-lsi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_pclk3: clk-pclk3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <104438965>; + }; + + clk_pclk4: clk-pclk4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <133250000>; + }; + + clk_pll4_p: clk-pll4_p { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + clk_pll4_r: clk-pll4_r { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <99000000>; + }; + }; + + intc: interrupt-controller@a0021000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xa0021000 0x1000>, + <0xa0022000 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + uart4: serial@40010000 { + compatible = "st,stm32h7-uart"; + reg = <0x40010000 0x400>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_hsi>; + status = "disabled"; + }; + + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&clk_pclk4>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + syscfg: syscon@50020000 { + compatible = "st,stm32mp157-syscfg", "syscon"; + reg = <0x50020000 0x400>; + clocks = <&clk_pclk3>; + }; + + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_pclk4>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + iwdg2: watchdog@5a002000 { + compatible = "st,stm32mp1-iwdg"; + reg = <0x5a002000 0x400>; + clocks = <&clk_pclk4>, <&clk_lsi>; + clock-names = "pclk", "lsi"; + status = "disabled"; + }; + + bsec: efuse@5c005000 { + compatible = "st,stm32mp13-bsec"; + reg = <0x5c005000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp: part_number_otp@4 { + reg = <0x4 0x2>; + }; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; + }; + + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. + */ + pinctrl: pin-controller@50002000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp135-pinctrl"; + ranges = <0 0x50002000 0x8400>; + pins-are-numbered; + + gpioa: gpio@50002000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOA"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@50003000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x1000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOB"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@50004000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x2000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOC"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@50005000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x3000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOD"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@50006000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x4000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOE"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@50007000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOF"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@50008000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x6000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOG"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@50009000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x7000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOH"; + ngpios = <15>; + gpio-ranges = <&pinctrl 0 112 15>; + }; + + gpioi: gpio@5000a000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x8000 0x400>; + clocks = <&clk_pclk4>; + st,bank-name = "GPIOI"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 128 8>; + }; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi new file mode 100644 index 0000000..0fb1386 --- /dev/null +++ b/arch/arm/dts/stm32mp133.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +#include "stm32mp131.dtsi" + +/ { + soc { + m_can1: can@4400e000 { + compatible = "bosch,m_can"; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clk_hse>, <&clk_pll4_r>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + status = "disabled"; + }; + + m_can2: can@4400f000 { + compatible = "bosch,m_can"; + reg = <0x4400f000 0x400>, <0x44011000 0x2800>; + reg-names = "m_can", "message_ram"; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int0", "int1"; + clocks = <&clk_hse>, <&clk_pll4_r>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp135.dtsi b/arch/arm/dts/stm32mp135.dtsi new file mode 100644 index 0000000..abf2acd --- /dev/null +++ b/arch/arm/dts/stm32mp135.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +#include "stm32mp133.dtsi" + +/ { + soc { + }; +}; diff --git a/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi new file mode 100644 index 0000000..dfe5bbb --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dk-u-boot.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include "stm32mp13-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + }; + + config { + u-boot,mmc-env-partition = "u-boot-env"; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_a { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts new file mode 100644 index 0000000..ee100d1 --- /dev/null +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &uart4; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + vdd_sd: vdd-sd { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp13xc.dtsi b/arch/arm/dts/stm32mp13xc.dtsi new file mode 100644 index 0000000..fa6889e --- /dev/null +++ b/arch/arm/dts/stm32mp13xc.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_axi>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/stm32mp13xf.dtsi b/arch/arm/dts/stm32mp13xf.dtsi new file mode 100644 index 0000000..fa6889e --- /dev/null +++ b/arch/arm/dts/stm32mp13xf.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. + */ + +/ { + soc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_axi>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index f9a583a..d9e2640 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -9,7 +9,7 @@ choice config TARGET_STIH410_B2260 bool "96Boards STiH410-B2260" help - Support for 96Board STiH410-B2260 based on STMicrolectronics + Support for 96Board STiH410-B2260 based on STMicroelectronics STiH410 soc. This board complies with 96Board Open Platform Specifications. Features: - 1GB DDR diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index e48f98b..db47bab 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -33,6 +33,28 @@ config SYS_MALLOC_LEN config ENV_SIZE default 0x2000 +choice + prompt "Select STMicroelectronics STM32MPxxx Soc" + default STM32MP15x + +config STM32MP13x + bool "Support STMicroelectronics STM32MP13x Soc" + select ARM_SMCCC + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select OF_BOARD + select OF_BOARD_SETUP + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + imply CMD_NVEDIT_INFO + help + support of STMicroelectronics SOC STM32MP13x family + STMicroelectronics MPU with core ARMv7 + config STM32MP15x bool "Support STMicroelectronics STM32MP15x Soc" select ARCH_SUPPORT_PSCI @@ -46,6 +68,7 @@ config STM32MP15x select STM32_RCC select STM32_RESET select STM32_SERIAL + select SUPPORT_SPL select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO help @@ -53,92 +76,8 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 - target all the STMicroelectronics board with SOC STM32MP1 family - -config STM32MP15x_STM32IMAGE - bool "Support STM32 image for generated U-Boot image" - depends on STM32MP15x && TFABOOT - help - Support of STM32 image generation for SOC STM32MP15x - for TF-A boot when FIP container is not used - -choice - prompt "STM32MP15x board select" - optional - -config TARGET_ST_STM32MP15x - bool "STMicroelectronics STM32MP15x boards" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - target the STMicroelectronics board with SOC STM32MP15x - managed by board/st/stm32mp1: - Evalulation board (EV1) or Discovery board (DK1 and DK2). - The difference between board are managed with devicetree - -config TARGET_MICROGEA_STM32MP1 - bool "Engicam MicroGEA STM32MP1 SOM" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. - - MicroGEA STM32MP1 MicroDev 2.0: - * MicroDev 2.0 is a general purpose miniature carrier board with CAN, - LTE and LVDS panel interfaces. - * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board - for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. - - MicroGEA STM32MP1 MicroDev 2.0 7" OF: - * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS - panel and toucscreen. - * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with - pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" - Open Frame Solution board. - -config TARGET_ICORE_STM32MP1 - bool "Engicam i.Core STM32MP1 SOM" - select STM32MP15x - imply BOOTSTAGE - imply CMD_BOOTSTAGE - imply CMD_CLS if CMD_BMP - imply DISABLE_CONSOLE - imply PRE_CONSOLE_BUFFER - imply SILENT_CONSOLE - help - i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. - - i.Core STM32MP1 EDIMM2.2: - * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. - * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for - creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. - - i.Core STM32MP1 C.TOUCH 2.0 - * C.TOUCH 2.0 is a general purpose Carrier board. - * i.Core STM32MP1 needs to mount on top of this Carrier board - for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. - -config TARGET_DH_STM32MP1_PDK2 - bool "DH STM32MP1 PDK2" - select STM32MP15x - help - Target the DH PDK2 development kit with STM32MP15x SoM. - endchoice -config SYS_TEXT_BASE - default 0xC0100000 - config NR_DRAM_BANKS default 1 @@ -164,7 +103,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 config STM32_ETZPC bool "STM32 Extended TrustZone Protection" - depends on STM32MP15x + depends on STM32MP15x || STM32MP13x default y imply BOOTP_SERVERIP help @@ -187,41 +126,8 @@ config CMD_STM32KEY This command is used to evaluate the secure boot on stm32mp SOC, it is deactivated by default in real products. -config PRE_CON_BUF_ADDR - default 0xC02FF000 - -config PRE_CON_BUF_SZ - default 4096 - -config BOOTSTAGE_STASH_ADDR - default 0xC3000000 - -if BOOTCOUNT_GENERIC -config SYS_BOOTCOUNT_SINGLEWORD - default y - -# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) -config SYS_BOOTCOUNT_ADDR - default 0x5C00A154 -endif - -if DEBUG_UART - -config DEBUG_UART_BOARD_INIT - default y - -# debug on UART4 by default -config DEBUG_UART_BASE - default 0x40010000 - -# clock source is HSI on reset -config DEBUG_UART_CLOCK - default 64000000 -endif +source "arch/arm/mach-stm32mp/Kconfig.13x" +source "arch/arm/mach-stm32mp/Kconfig.15x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" -source "board/dhelectronics/dh_stm32mp1/Kconfig" -source "board/engicam/stm32mp1/Kconfig" -source "board/st/stm32mp1/Kconfig" - endif diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x new file mode 100644 index 0000000..5fc0009 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -0,0 +1,57 @@ +if STM32MP13x + +choice + prompt "STM32MP13x board select" + optional + +config TARGET_ST_STM32MP13x + bool "STMicroelectronics STM32MP13x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP13x + managed by board/st/stm32mp1. + The difference between board are managed with devicetree + +endchoice + +config SYS_TEXT_BASE + default 0xC0000000 + +config PRE_CON_BUF_ADDR + default 0xC0800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0xC3000000 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(31) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A17C +endif + +if DEBUG_UART + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 48000000 if STM32_FPGA + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Kconfig.15x b/arch/arm/mach-stm32mp/Kconfig.15x new file mode 100644 index 0000000..d516270 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.15x @@ -0,0 +1,135 @@ +if STM32MP15x + +config STM32MP15x_STM32IMAGE + bool "Support STM32 image for generated U-Boot image" + depends on TFABOOT + help + Support of STM32 image generation for SOC STM32MP15x + for TF-A boot when FIP container is not used + +choice + prompt "STM32MP15x board select" + optional + +config TARGET_ST_STM32MP15x + bool "STMicroelectronics STM32MP15x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + target the STMicroelectronics board with SOC STM32MP15x + managed by board/st/stm32mp1: + Evalulation board (EV1) or Discovery board (DK1 and DK2). + The difference between board are managed with devicetree + +config TARGET_DH_STM32MP1_PDK2 + bool "DH STM32MP1 PDK2" + help + Target the DH PDK2 development kit with STM32MP15x SoM. + +config TARGET_MICROGEA_STM32MP1 + bool "Engicam MicroGEA STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. + + MicroGEA STM32MP1 MicroDev 2.0: + * MicroDev 2.0 is a general purpose miniature carrier board with CAN, + LTE and LVDS panel interfaces. + * MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board + for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. + + MicroGEA STM32MP1 MicroDev 2.0 7" OF: + * 7" OF is a capacitive touch 7" Open Frame panel solutions with LVDS + panel and toucscreen. + * MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with + pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" + Open Frame Solution board. + +config TARGET_ICORE_STM32MP1 + bool "Engicam i.Core STM32MP1 SOM" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + imply CMD_CLS if CMD_BMP + imply DISABLE_CONSOLE + imply PRE_CONSOLE_BUFFER + imply SILENT_CONSOLE + help + i.Core STM32MP1 is an EDIMM SOM based on STM32MP157A. + + i.Core STM32MP1 EDIMM2.2: + * EDIMM2.2 is a Form Factor Capacitive Evaluation Board. + * i.Core STM32MP1 needs to mount on top of EDIMM2.2 for + creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. + + i.Core STM32MP1 C.TOUCH 2.0 + * C.TOUCH 2.0 is a general purpose Carrier board. + * i.Core STM32MP1 needs to mount on top of this Carrier board + for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. + +endchoice + +config STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR" + depends on DM_REGULATOR && DM_PMIC + default y + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. + +config SPL_STM32MP15_PWR + bool "Enable driver for STM32MP15x PWR in SPL" + depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC + default y + help + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. + +config SYS_TEXT_BASE + default 0xC0100000 + +config PRE_CON_BUF_ADDR + default 0xC02FF000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0xC3000000 + +if BOOTCOUNT_GENERIC +config SYS_BOOTCOUNT_SINGLEWORD + default y + +# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) +config SYS_BOOTCOUNT_ADDR + default 0x5C00A154 +endif + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on UART4 by default +config DEBUG_UART_BASE + default 0x40010000 + +# clock source is HSI on reset +config DEBUG_UART_CLOCK + default 64000000 +endif + +source "board/st/stm32mp1/Kconfig" +source "board/dhelectronics/dh_stm32mp1/Kconfig" +source "board/engicam/stm32mp1/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 391b47c..1db9057 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -8,6 +8,9 @@ obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-y += tzc400.o @@ -19,5 +22,5 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif -obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 506caa0..c00130b 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -632,3 +632,20 @@ bool bsec_dbgswenable(void) return false; } + +u32 get_otp(int index, int shift, int mask) +{ + int ret; + struct udevice *dev; + u32 otp = 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + + if (!ret) + ret = misc_read(dev, STM32_BSEC_SHADOW(index), + &otp, sizeof(otp)); + + return (otp >> shift) & mask; +} diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 0ad5f30..855fc75 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -16,7 +16,6 @@ #include <misc.h> #include <net.h> #include <asm/io.h> -#include <asm/arch/bsec.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> @@ -24,67 +23,6 @@ #include <dm/uclass.h> #include <linux/bitops.h> -/* RCC register */ -#define RCC_TZCR (STM32_RCC_BASE + 0x00) -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) -#define RCC_BDCR (STM32_RCC_BASE + 0x0140) -#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) -#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) -#define RCC_BDCR_VSWRST BIT(31) -#define RCC_BDCR_RTCSRC GENMASK(17, 16) -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* Security register */ -#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) -#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) - -#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) -#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) -#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) - -#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) - -#define PWR_CR1 (STM32_PWR_BASE + 0x00) -#define PWR_MCUCR (STM32_PWR_BASE + 0x14) -#define PWR_CR1_DBP BIT(8) -#define PWR_MCUCR_SBF BIT(6) - -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -/* GPIOZ registers */ -#define GPIOZ_SECCFGR 0x54004030 - -/* boot interface from Bootrom - * - boot instance = bit 31:16 - * - boot device = bit 15:0 - */ -#define BOOTROM_PARAM_ADDR 0x2FFC0078 -#define BOOTROM_MODE_MASK GENMASK(15, 0) -#define BOOTROM_MODE_SHIFT 0 -#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) -#define BOOTROM_INSTANCE_SHIFT 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - -/* Package = bit 27:29 of OTP16 - * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm - * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm - * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm - * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm - * - others: Reserved - */ -#define PKG_SHIFT 27 -#define PKG_MASK GENMASK(2, 0) - /* * early TLB into the .data section so that it not get cleared * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) @@ -93,121 +31,6 @@ u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); struct lmb lmb; -static void security_init(void) -{ - /* Disable the backup domain write protection */ - /* the protection is enable at each reset by hardware */ - /* And must be disable by software */ - setbits_le32(PWR_CR1, PWR_CR1_DBP); - - while (!(readl(PWR_CR1) & PWR_CR1_DBP)) - ; - - /* If RTC clock isn't enable so this is a cold boot then we need - * to reset the backup domain - */ - if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { - setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) - ; - clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - } - - /* allow non secure access in Write/Read for all peripheral */ - writel(GENMASK(25, 0), ETZPC_DECPROT0); - - /* Open SYSRAM for no secure access */ - writel(0x0, ETZPC_TZMA1_SIZE); - - /* enable TZC1 TZC2 clock */ - writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); - - /* Region 0 set to no access by default */ - /* bit 0 / 16 => nsaid0 read/write Enable - * bit 1 / 17 => nsaid1 read/write Enable - * ... - * bit 15 / 31 => nsaid15 read/write Enable - */ - writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); - /* bit 30 / 31 => Secure Global Enable : write/read */ - /* bit 0 / 1 => Region Enable for filter 0/1 */ - writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); - - /* Enable Filter 0 and 1 */ - setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); - - /* RCC trust zone deactivated */ - writel(0x0, RCC_TZCR); - - /* TAMP: deactivate the internal tamper - * Bit 23 ITAMP8E: monotonic counter overflow - * Bit 20 ITAMP5E: RTC calendar overflow - * Bit 19 ITAMP4E: HSE monitoring - * Bit 18 ITAMP3E: LSE monitoring - * Bit 16 ITAMP1E: RTC power domain supply monitoring - */ - writel(0x0, TAMP_CR1); - - /* GPIOZ: deactivate the security */ - writel(BIT(0), RCC_MP_AHB5ENSETR); - writel(0x0, GPIOZ_SECCFGR); -} - -/* - * Debug init - */ -static void dbgmcu_init(void) -{ - /* - * Freeze IWDG2 if Cortex-A7 is in debug mode - * done in TF-A for TRUSTED boot and - * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE - */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); - } -} - -void spl_board_init(void) -{ - struct udevice *dev; - int ret; - - dbgmcu_init(); - - /* force probe of BSEC driver to shadow the upper OTP */ - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); - if (ret) - log_warning("BSEC probe failed: %d\n", ret); -} - -/* get bootmode from ROM code boot context: saved in TAMP register */ -static void update_bootmode(void) -{ - u32 boot_mode; - u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); - u32 bootrom_device, bootrom_instance; - - /* enable TAMP clock = RTCAPBEN */ - writel(BIT(8), RCC_MP_APB5ENSETR); - - /* read bootrom context */ - bootrom_device = - (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; - bootrom_instance = - (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; - boot_mode = - ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | - ((bootrom_instance << BOOT_INSTANCE_SHIFT) & - BOOT_INSTANCE_MASK); - - /* save the boot mode in TAMP backup register */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, - TAMP_BOOT_MODE_MASK, - boot_mode << TAMP_BOOT_MODE_SHIFT); -} - u32 get_bootmode(void) { /* read bootmode from TAMP backup register */ @@ -229,8 +52,11 @@ void dram_bank_mmu_setup(int bank) enum dcache_option option; if (IS_ENABLED(CONFIG_SPL_BUILD)) { +/* STM32_SYSRAM_BASE exist only when SPL is supported */ +#ifdef CONFIG_SPL start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); +#endif } else if (gd->flags & GD_FLG_RELOC) { /* bd->bi_dram is available only after relocation */ start = bd->bi_dram[bank].start; @@ -277,25 +103,24 @@ static void early_enable_caches(void) */ int arch_cpu_init(void) { - u32 boot_mode; - early_enable_caches(); /* early armv7 timer init: needed for polling */ timer_init(); - if (IS_ENABLED(CONFIG_SPL_BUILD)) { - security_init(); - update_bootmode(); - } -/* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { - /* Reset Coprocessor state unless it wakes up from Standby power mode */ - if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { - writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); - writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); - } - } + return 0; +} + +/* weak function for SOC specific initialization */ +__weak void stm32mp_cpu_init(void) +{ +} + +int mach_cpu_init(void) +{ + u32 boot_mode; + + stm32mp_cpu_init(); boot_mode = get_bootmode(); @@ -324,139 +149,6 @@ void enable_caches(void) dcache_enable(); } -static u32 read_idc(void) -{ - /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - - return readl(DBGMCU_IDC); - } - - if (CONFIG_IS_ENABLED(STM32MP15x)) - return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ - else - return 0x0; -} - -u32 get_cpu_dev(void) -{ - return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; -} - -static u32 get_otp(int index, int shift, int mask) -{ - int ret; - struct udevice *dev; - u32 otp = 0; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(stm32mp_bsec), - &dev); - - if (!ret) - ret = misc_read(dev, STM32_BSEC_SHADOW(index), - &otp, sizeof(otp)); - - return (otp >> shift) & mask; -} - -/* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -u32 get_cpu_type(void) -{ - return (get_cpu_dev() << 16) | get_cpu_rpn(); -} - -/* Get Package options from OTP */ -u32 get_cpu_package(void) -{ - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); -} - -static const char * const soc_type[] = { - "????", - "151C", "151A", "151F", "151D", - "153C", "153A", "153F", "153D", - "157C", "157A", "157F", "157D" -}; - -static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; -static const char * const soc_rev[] = { "?", "A", "B", "Z" }; - -static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, - unsigned int *rev) -{ - u32 cpu_type = get_cpu_type(); - u32 ct = cpu_type & ~(BIT(7) | BIT(0)); - u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); - u32 cp = get_cpu_package(); - - /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ - switch (ct) { - case CPU_STM32MP151Cxx: - *type = cm + 1; - break; - case CPU_STM32MP153Cxx: - *type = cm + 5; - break; - case CPU_STM32MP157Cxx: - *type = cm + 9; - break; - default: - *type = 0; - break; - } - - /* Package */ - switch (cp) { - case PKG_AA_LBGA448: - case PKG_AB_LBGA354: - case PKG_AC_TFBGA361: - case PKG_AD_TFBGA257: - *pkg = cp; - break; - default: - *pkg = 0; - break; - } - - /* Revision */ - switch (get_cpu_rev()) { - case CPU_REV1: - *rev = 1; - break; - case CPU_REV2: - *rev = 2; - break; - case CPU_REV2_1: - *rev = 3; - break; - default: - *rev = 0; - break; - } -} - -void get_soc_name(char name[SOC_NAME_SIZE]) -{ - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); -} - /* used when CONFIG_DISPLAY_CPUINFO is activated */ int print_cpuinfo(void) { @@ -598,16 +290,18 @@ __weak int setup_mac_address(void) { int ret; int i; - u32 otp[2]; + u32 otp[3]; uchar enetaddr[6]; struct udevice *dev; + int nb_eth, nb_otp, index; if (!IS_ENABLED(CONFIG_NET)) return 0; - /* MAC already in environment */ - if (eth_env_get_enetaddr("ethaddr", enetaddr)) - return 0; + nb_eth = get_eth_nb(); + + /* 6 bytes for each MAC addr and 4 bytes for each OTP */ + nb_otp = DIV_ROUND_UP(6 * nb_eth, 4); ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), @@ -615,22 +309,31 @@ __weak int setup_mac_address(void) if (ret) return ret; - ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), - otp, sizeof(otp)); + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); if (ret < 0) return ret; - for (i = 0; i < 6; i++) - enetaddr[i] = ((uint8_t *)&otp)[i]; + for (index = 0; index < nb_eth; index++) { + /* MAC already in environment */ + if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) + continue; + + for (i = 0; i < 6; i++) + enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index]; - if (!is_valid_ethaddr(enetaddr)) { - log_err("invalid MAC address in OTP %pM\n", enetaddr); - return -EINVAL; + if (!is_valid_ethaddr(enetaddr)) { + log_err("invalid MAC address %d in OTP %pM\n", + index, enetaddr); + return -EINVAL; + } + log_debug("OTP MAC address %d = %pM\n", index, enetaddr); + ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); + if (ret) { + log_err("Failed to set mac address %pM from OTP: %d\n", + enetaddr, ret); + return ret; + } } - log_debug("OTP MAC address = %pM\n", enetaddr); - ret = eth_env_set_enetaddr("ethaddr", enetaddr); - if (ret) - log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret); return 0; } @@ -662,15 +365,8 @@ static int setup_serial_number(void) return 0; } -static void setup_soc_type_pkg_rev(void) +__weak void stm32mp_misc_init(void) { - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - env_set("soc_type", soc_type[type]); - env_set("soc_pkg", soc_pkg[pkg]); - env_set("soc_rev", soc_rev[rev]); } int arch_misc_init(void) @@ -678,7 +374,7 @@ int arch_misc_init(void) setup_boot_mode(); setup_mac_address(); setup_serial_number(); - setup_soc_type_pkg_rev(); + stm32mp_misc_init(); return 0; } diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index b1a4b76..3b4c05d 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,13 +28,120 @@ #define ETZPC_RESERVED 0xffffffff -#define STM32_FDCAN_BASE 0x4400e000 -#define STM32_CRYP2_BASE 0x4c005000 -#define STM32_CRYP1_BASE 0x54001000 -#define STM32_GPU_BASE 0x59000000 -#define STM32_DSI_BASE 0x5a000000 +#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000 + +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000 + +static const u32 stm32mp13_ip_addr[] = { + 0x50025000, /* 0 VREFBUF APB3 */ + 0x50021000, /* 1 LPTIM2 APB3 */ + 0x50022000, /* 2 LPTIM3 APB3 */ + STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ + 0x5A006000, /* 5 USBPHYCTRL APB4 */ + 0x5A003000, /* 6 DDRCTRLPHY APB4 */ + ETZPC_RESERVED, /* 7 Reserved*/ + ETZPC_RESERVED, /* 8 Reserved*/ + ETZPC_RESERVED, /* 9 Reserved*/ + 0x5C006000, /* 10 TZC APB5 */ + 0x58001000, /* 11 MCE APB5 */ + 0x5C000000, /* 12 IWDG1 APB5 */ + 0x5C008000, /* 13 STGENC APB5 */ + ETZPC_RESERVED, /* 14 Reserved*/ + ETZPC_RESERVED, /* 15 Reserved*/ + 0x4C000000, /* 16 USART1 APB6 */ + 0x4C001000, /* 17 USART2 APB6 */ + 0x4C002000, /* 18 SPI4 APB6 */ + 0x4C003000, /* 19 SPI5 APB6 */ + 0x4C004000, /* 20 I2C3 APB6 */ + 0x4C005000, /* 21 I2C4 APB6 */ + 0x4C006000, /* 22 I2C5 APB6 */ + 0x4C007000, /* 23 TIM12 APB6 */ + 0x4C008000, /* 24 TIM13 APB6 */ + 0x4C009000, /* 25 TIM14 APB6 */ + 0x4C00A000, /* 26 TIM15 APB6 */ + 0x4C00B000, /* 27 TIM16 APB6 */ + 0x4C00C000, /* 28 TIM17 APB6 */ + ETZPC_RESERVED, /* 29 Reserved*/ + ETZPC_RESERVED, /* 30 Reserved*/ + ETZPC_RESERVED, /* 31 Reserved*/ + STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ + 0x48004000, /* 33 ADC2 AHB2 */ + 0x49000000, /* 34 OTG AHB2 */ + ETZPC_RESERVED, /* 35 Reserved*/ + ETZPC_RESERVED, /* 36 Reserved*/ + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ + ETZPC_RESERVED, /* 38 Reserved*/ + ETZPC_RESERVED, /* 39 Reserved*/ + 0x54004000, /* 40 RNG AHB5 */ + 0x54003000, /* 41 HASH AHB5 */ + STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ + 0x54005000, /* 43 SAES AHB5 */ + 0x54006000, /* 44 PKA AHB5 */ + 0x54000000, /* 45 BKPSRAM AHB5 */ + ETZPC_RESERVED, /* 46 Reserved*/ + ETZPC_RESERVED, /* 47 Reserved*/ + 0x5800A000, /* 48 ETH1 AHB6 */ + STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ + 0x58005000, /* 50 SDMMC1 AHB6 */ + 0x58007000, /* 51 SDMMC2 AHB6 */ + ETZPC_RESERVED, /* 52 Reserved*/ + ETZPC_RESERVED, /* 53 Reserved*/ + 0x58002000, /* 54 FMC AHB6 */ + 0x58003000, /* 55 QSPI AHB6 */ + ETZPC_RESERVED, /* 56 Reserved*/ + ETZPC_RESERVED, /* 57 Reserved*/ + ETZPC_RESERVED, /* 58 Reserved*/ + ETZPC_RESERVED, /* 59 Reserved*/ + 0x30000000, /* 60 SRAM1 MLAHB */ + 0x30004000, /* 61 SRAM2 MLAHB */ + 0x30006000, /* 62 SRAM3 MLAHB */ + ETZPC_RESERVED, /* 63 Reserved*/ + ETZPC_RESERVED, /* 64 Reserved*/ + ETZPC_RESERVED, /* 65 Reserved*/ + ETZPC_RESERVED, /* 66 Reserved*/ + ETZPC_RESERVED, /* 67 Reserved*/ + ETZPC_RESERVED, /* 68 Reserved*/ + ETZPC_RESERVED, /* 69 Reserved*/ + ETZPC_RESERVED, /* 70 Reserved*/ + ETZPC_RESERVED, /* 71 Reserved*/ + ETZPC_RESERVED, /* 72 Reserved*/ + ETZPC_RESERVED, /* 73 Reserved*/ + ETZPC_RESERVED, /* 74 Reserved*/ + ETZPC_RESERVED, /* 75 Reserved*/ + ETZPC_RESERVED, /* 76 Reserved*/ + ETZPC_RESERVED, /* 77 Reserved*/ + ETZPC_RESERVED, /* 78 Reserved*/ + ETZPC_RESERVED, /* 79 Reserved*/ + ETZPC_RESERVED, /* 80 Reserved*/ + ETZPC_RESERVED, /* 81 Reserved*/ + ETZPC_RESERVED, /* 82 Reserved*/ + ETZPC_RESERVED, /* 83 Reserved*/ + ETZPC_RESERVED, /* 84 Reserved*/ + ETZPC_RESERVED, /* 85 Reserved*/ + ETZPC_RESERVED, /* 86 Reserved*/ + ETZPC_RESERVED, /* 87 Reserved*/ + ETZPC_RESERVED, /* 88 Reserved*/ + ETZPC_RESERVED, /* 89 Reserved*/ + ETZPC_RESERVED, /* 90 Reserved*/ + ETZPC_RESERVED, /* 91 Reserved*/ + ETZPC_RESERVED, /* 92 Reserved*/ + ETZPC_RESERVED, /* 93 Reserved*/ + ETZPC_RESERVED, /* 94 Reserved*/ + ETZPC_RESERVED, /* 95 Reserved*/ +}; -static const u32 stm32mp1_ip_addr[] = { +static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ 0x5c003000, /* 02 iwdg1 */ @@ -44,7 +151,7 @@ static const u32 stm32mp1_ip_addr[] = { ETZPC_RESERVED, /* 06 reserved */ 0x54003000, /* 07 rng1 */ 0x54002000, /* 08 hash1 */ - STM32_CRYP1_BASE, /* 09 cryp1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ 0x5a003000, /* 0A ddrctrl */ 0x5a004000, /* 0B ddrphyc */ 0x5c009000, /* 0C i2c6 */ @@ -97,7 +204,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x4400b000, /* 3B sai2 */ 0x4400c000, /* 3C sai3 */ 0x4400d000, /* 3D dfsdm */ - STM32_FDCAN_BASE, /* 3E tt_fdcan */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ ETZPC_RESERVED, /* 3F reserved */ 0x50021000, /* 40 lptim2 */ 0x50022000, /* 41 lptim3 */ @@ -110,7 +217,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x48003000, /* 48 adc */ 0x4c002000, /* 49 hash2 */ 0x4c003000, /* 4A rng2 */ - STM32_CRYP2_BASE, /* 4B cryp2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ ETZPC_RESERVED, /* 4C reserved */ ETZPC_RESERVED, /* 4D reserved */ ETZPC_RESERVED, /* 4E reserved */ @@ -163,8 +270,15 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB]; - array = stm32mp1_ip_addr; - array_size = ARRAY_SIZE(stm32mp1_ip_addr); + if (IS_ENABLED(CONFIG_STM32MP13x)) { + array = stm32mp13_ip_addr; + array_size = ARRAY_SIZE(stm32mp13_ip_addr); + } + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + } for (i = 0; i < ETZPC_DECPROT_NB; i++) decprot[i] = readl(ETZPC_DECPROT(i)); @@ -248,33 +362,46 @@ static void stm32_fdt_disable_optee(void *blob) } } -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, struct bd_info *bd) +static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { - int ret = 0; - int soc; - u32 pkg, cpu; - char name[SOC_NAME_SIZE]; - - soc = fdt_path_offset(blob, "/soc"); - /* when absent, nothing to do */ - if (soc == -FDT_ERR_NOTFOUND) - return 0; - if (soc < 0) - return soc; + switch (cpu) { + case CPU_STM32MP131Fxx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Cxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); + stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); + fallthrough; + case CPU_STM32MP133Fxx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Cxx: + case CPU_STM32MP133Axx: + stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); + stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", + name); + stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); + break; + default: + break; + } - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; + switch (cpu) { + case CPU_STM32MP135Dxx: + case CPU_STM32MP135Axx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Axx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); + break; + default: + break; } +} - /* MPUs Part Numbers and name*/ - cpu = get_cpu_type(); - get_soc_name(name); +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + u32 pkg; switch (cpu) { case CPU_STM32MP151Fxx: @@ -284,19 +411,18 @@ int ft_system_setup(void *blob, struct bd_info *bd) stm32_fdt_fixup_cpu(blob, name); /* after cpu delete we can't trust the soc offsets anymore */ soc = fdt_path_offset(blob, "/soc"); - stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); - /* fall through */ + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; case CPU_STM32MP153Fxx: case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx: - stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); - stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name); + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); break; default: break; } - switch (cpu) { case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx: @@ -304,24 +430,25 @@ int ft_system_setup(void *blob, struct bd_info *bd) case CPU_STM32MP153Axx: case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx: - stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); - stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); break; default: break; } - switch (get_cpu_package()) { - case PKG_AA_LBGA448: + case STM32MP15_PKG_AA_LBGA448: pkg = STM32MP_PKG_AA; break; - case PKG_AB_LBGA354: + case STM32MP15_PKG_AB_LBGA354: pkg = STM32MP_PKG_AB; break; - case PKG_AC_TFBGA361: + case STM32MP15_PKG_AC_TFBGA361: pkg = STM32MP_PKG_AC; break; - case PKG_AD_TFBGA257: + case STM32MP15_PKG_AD_TFBGA257: pkg = STM32MP_PKG_AD; break; default: @@ -334,18 +461,54 @@ int ft_system_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", "st,package", pkg, false); } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + } + + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); - /* - * TEMP: remove OP-TEE nodes in kernel device tree - * copied from U-Boot device tree by optee_copy_fdt_nodes - * when OP-TEE is not detected (probe failed) - * these OP-TEE nodes are present in <board>-u-boot.dtsi - * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility - * when FIP is not used by TF-A - */ - if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && - !tee_find_device(NULL, NULL, NULL, NULL)) - stm32_fdt_disable_optee(blob); + if (IS_ENABLED(CONFIG_STM32MP13x)) + stm32mp13_fdt_fixup(blob, soc, cpu, name); + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in <board>-u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + } return ret; } diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 47e88fc..c70375a 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -17,7 +17,9 @@ #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 +#ifdef CONFIG_STM32MP15x #define STM32_DBGMCU_BASE 0x50081000 +#endif #define STM32_FMC2_BASE 0x58002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 @@ -26,8 +28,14 @@ #define STM32_STGEN_BASE 0x5C008000 #define STM32_TAMP_BASE 0x5C00A000 +#ifdef CONFIG_STM32MP15x #define STM32_USART1_BASE 0x5C000000 #define STM32_USART2_BASE 0x4000E000 +#endif +#ifdef CONFIG_STM32MP13x +#define STM32_USART1_BASE 0x4c000000 +#define STM32_USART2_BASE 0x4c001000 +#endif #define STM32_USART3_BASE 0x4000F000 #define STM32_UART4_BASE 0x40010000 #define STM32_UART5_BASE 0x40011000 @@ -39,8 +47,10 @@ #define STM32_SDMMC2_BASE 0x58007000 #define STM32_SDMMC3_BASE 0x48004000 +#ifdef CONFIG_STM32MP15x #define STM32_SYSRAM_BASE 0x2FFC0000 #define STM32_SYSRAM_SIZE SZ_256K +#endif #define STM32_DDR_BASE 0xC0000000 #define STM32_DDR_SIZE SZ_1G @@ -98,6 +108,8 @@ enum boot_device { /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) + +#ifdef CONFIG_STM32MP15x #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_COPRO_RSC_TBL_ADDRESS TAMP_BACKUP_REGISTER(17) @@ -111,13 +123,18 @@ enum boot_device { #define TAMP_COPRO_STATE_CSTOP 3 #define TAMP_COPRO_STATE_STANDBY 4 #define TAMP_COPRO_STATE_CRASH 5 +#endif + +#ifdef CONFIG_STM32MP13x +#define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) +#endif #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) #define TAMP_BOOT_MODE_SHIFT 8 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) -#define TAMP_BOOT_DEBUG_ON BIT(16) enum forced_boot_mode { BOOT_NORMAL = 0x00, @@ -138,11 +155,19 @@ enum forced_boot_mode { #define STM32_BSEC_LOCK(id) (STM32_BSEC_LOCK_OFFSET + (id) * 4) /* BSEC OTP index */ +#ifdef CONFIG_STM32MP15x #define BSEC_OTP_RPN 1 #define BSEC_OTP_SERIAL 13 #define BSEC_OTP_PKG 16 #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 59 +#endif +#ifdef CONFIG_STM32MP13x +#define BSEC_OTP_RPN 1 +#define BSEC_OTP_SERIAL 13 +#define BSEC_OTP_MAC 57 +#define BSEC_OTP_BOARD 60 +#endif #endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index b91f98e..4b564e8 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -3,7 +3,7 @@ * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved */ -/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0) */ +/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */ #define CPU_STM32MP157Cxx 0x05000000 #define CPU_STM32MP157Axx 0x05000001 #define CPU_STM32MP153Cxx 0x05000024 @@ -17,10 +17,24 @@ #define CPU_STM32MP151Fxx 0x050000AE #define CPU_STM32MP151Dxx 0x050000AF +#define CPU_STM32MP135Cxx 0x05010000 +#define CPU_STM32MP135Axx 0x05010001 +#define CPU_STM32MP133Cxx 0x050100C0 +#define CPU_STM32MP133Axx 0x050100C1 +#define CPU_STM32MP131Cxx 0x050106C8 +#define CPU_STM32MP131Axx 0x050106C9 +#define CPU_STM32MP135Fxx 0x05010800 +#define CPU_STM32MP135Dxx 0x05010801 +#define CPU_STM32MP133Fxx 0x050108C0 +#define CPU_STM32MP133Dxx 0x050108C1 +#define CPU_STM32MP131Fxx 0x05010EC8 +#define CPU_STM32MP131Dxx 0x05010EC9 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 +#define CPU_DEV_STM32MP13 0x501 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -36,10 +50,12 @@ u32 get_cpu_rev(void); /* Get Package options from OTP */ u32 get_cpu_package(void); -#define PKG_AA_LBGA448 4 -#define PKG_AB_LBGA354 3 -#define PKG_AC_TFBGA361 2 -#define PKG_AD_TFBGA257 1 +/* package used for STM32MP15x */ +#define STM32MP15_PKG_AA_LBGA448 4 +#define STM32MP15_PKG_AB_LBGA354 3 +#define STM32MP15_PKG_AC_TFBGA361 2 +#define STM32MP15_PKG_AD_TFBGA257 1 +#define STM32MP15_PKG_UNKNOWN 0 /* Get SOC name */ #define SOC_NAME_SIZE 20 @@ -48,7 +64,15 @@ void get_soc_name(char name[SOC_NAME_SIZE]); /* return boot mode */ u32 get_bootmode(void); +int get_eth_nb(void); int setup_mac_address(void); /* board power management : configure vddcore according OPP */ void board_vddcore_init(u32 voltage_mv); + +/* weak function */ +void stm32mp_cpu_init(void); +void stm32mp_misc_init(void); + +/* helper function: read data from OTP */ +u32 get_otp(int index, int shift, int mask); diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 78fa9d7..19d9fe0 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -190,6 +190,7 @@ void board_init_f(ulong dummy) int ret; arch_cpu_init(); + mach_cpu_init(); ret = spl_early_init(); if (ret) { diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c new file mode 100644 index 0000000..bd3f24c --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp13x.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <common.h> +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_IDC_OFFSET 0x380 +#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_IDC_DEV_ID_SHIFT 0 +#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_IDC_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(11, 0) + +static u32 read_idc(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_IDC_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + int nb_eth = 2; + + switch (get_cpu_type()) { + case CPU_STM32MP131Dxx: + fallthrough; + case CPU_STM32MP131Cxx: + fallthrough; + case CPU_STM32MP131Axx: + nb_eth = 1; + break; + default: + nb_eth = 2; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r; + + /* MPUs Part Numbers */ + switch (get_cpu_type()) { + case CPU_STM32MP135Fxx: + cpu_s = "135F"; + break; + case CPU_STM32MP135Dxx: + cpu_s = "135D"; + break; + case CPU_STM32MP135Cxx: + cpu_s = "135C"; + break; + case CPU_STM32MP135Axx: + cpu_s = "135A"; + break; + case CPU_STM32MP133Fxx: + cpu_s = "133F"; + break; + case CPU_STM32MP133Dxx: + cpu_s = "133D"; + break; + case CPU_STM32MP133Cxx: + cpu_s = "133C"; + break; + case CPU_STM32MP133Axx: + cpu_s = "133A"; + break; + case CPU_STM32MP131Fxx: + cpu_s = "131F"; + break; + case CPU_STM32MP131Dxx: + cpu_s = "131D"; + break; + case CPU_STM32MP131Cxx: + cpu_s = "131C"; + break; + case CPU_STM32MP131Axx: + cpu_s = "131A"; + break; + default: + cpu_s = "????"; + break; + } + + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + case CPU_REV1_1: + cpu_r = "Z"; + break; + default: + cpu_r = "?"; + break; + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c new file mode 100644 index 0000000..a093e61 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <common.h> +#include <env.h> +#include <log.h> +#include <asm/io.h> +#include <asm/arch/bsec.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) +#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) +#define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) + +/* GPIOZ registers */ +#define GPIOZ_SECCFGR 0x54004030 + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_PARAM_ADDR 0x2FFC0078 +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines + * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm + * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm + * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm + * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 27 +#define PKG_MASK GENMASK(2, 0) + +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(GENMASK(25, 0), ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable TZC1 TZC2 clock */ + writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); + /* bit 30 / 31 => Secure Global Enable : write/read */ + /* bit 0 / 1 => Region Enable for filter 0/1 */ + writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); + + /* Enable Filter 0 and 1 */ + setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); + + /* GPIOZ: deactivate the security */ + writel(BIT(0), RCC_MP_AHB5ENSETR); + writel(0x0, GPIOZ_SECCFGR); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + security_init(); + update_bootmode(); + } + + /* reset copro state in SPL, when used, or in U-Boot */ + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } + } +} + +static u32 read_idc(void) +{ + /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); + } + + return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + return 1; +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +static const char * const soc_type[] = { + "????", + "151C", "151A", "151F", "151D", + "153C", "153A", "153F", "153D", + "157C", "157A", "157F", "157D" +}; + +static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z" }; + +static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, + unsigned int *rev) +{ + u32 cpu_type = get_cpu_type(); + u32 ct = cpu_type & ~(BIT(7) | BIT(0)); + u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); + u32 cp = get_cpu_package(); + + /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ + switch (ct) { + case CPU_STM32MP151Cxx: + *type = cm + 1; + break; + case CPU_STM32MP153Cxx: + *type = cm + 5; + break; + case CPU_STM32MP157Cxx: + *type = cm + 9; + break; + default: + *type = 0; + break; + } + + /* Package */ + switch (cp) { + case STM32MP15_PKG_AA_LBGA448: + case STM32MP15_PKG_AB_LBGA354: + case STM32MP15_PKG_AC_TFBGA361: + case STM32MP15_PKG_AD_TFBGA257: + *pkg = cp; + break; + default: + *pkg = 0; + break; + } + + /* Revision */ + switch (get_cpu_rev()) { + case CPU_REV1: + *rev = 1; + break; + case CPU_REV2: + *rev = 2; + break; + case CPU_REV2_1: + *rev = 3; + break; + default: + *rev = 0; + break; + } +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); +} + +static void setup_soc_type_pkg_rev(void) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + env_set("soc_type", soc_type[type]); + env_set("soc_pkg", soc_pkg[pkg]); + env_set("soc_rev", soc_rev[rev]); +} + +/* weak function called in arch_misc_init */ +void stm32mp_misc_init(void) +{ + setup_soc_type_pkg_rev(); +} |