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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2018-04-26 18:21:25 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-07 15:49:52 -0400 |
| commit | 2a5180535cb7c66ed3ca98d01db82df7c936b469 (patch) | |
| tree | b428362002187474ca14d4798c9eb86498a077c4 /arch | |
| parent | 04ca871459da53930a81509c53724ccfa7101118 (diff) | |
| download | u-boot-2a5180535cb7c66ed3ca98d01db82df7c936b469.zip u-boot-2a5180535cb7c66ed3ca98d01db82df7c936b469.tar.gz u-boot-2a5180535cb7c66ed3ca98d01db82df7c936b469.tar.bz2 | |
arm: v7: Update VBAR only if available
Not all ARM V7 based cpus has VBAR for remapping
vector base address. So, update VBAR only if it available.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f5df597..8c19a83 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -72,10 +72,12 @@ switch_to_hypervisor_ret: bic r0, #CR_V @ V = 0 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register +#ifdef CONFIG_HAS_VBAR /* Set vector address in CP15 VBAR register */ ldr r0, =_start mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif +#endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT |