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| author | Andre Przywara <andre.przywara@arm.com> | 2021-04-28 21:29:55 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-07-10 01:22:09 +0100 |
| commit | b8747854de7f4aaa8d8a60842c5a97358d4ad891 (patch) | |
| tree | 4600d51cf3dc6531a63d34eb596ca536845c35fb /arch | |
| parent | 212224ed68f12616bcdc5384dd87d6454dc68b57 (diff) | |
| download | u-boot-b8747854de7f4aaa8d8a60842c5a97358d4ad891.zip u-boot-b8747854de7f4aaa8d8a60842c5a97358d4ad891.tar.gz u-boot-b8747854de7f4aaa8d8a60842c5a97358d4ad891.tar.bz2 | |
sunxi: H616: Enable full 4GB of DRAM
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-sunxi/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/board.c | 11 |
2 files changed, 12 insertions, 3 deletions
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index bc8509b..8e7aa84 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -190,10 +190,10 @@ config MACH_SUNXI_H3_H5 select SUPPORT_SPL # TODO: try out A80's 8GiB DRAM space -# TODO: H616 supports 4 GiB DRAM space config SUNXI_DRAM_MAX_SIZE hex - default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 || MACH_SUN50I_H616 + default 0x100000000 if MACH_SUN50I_H616 + default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6 default 0x80000000 choice diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 9b84132..e979e42 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -56,7 +56,7 @@ static struct mm_region sunxi_mem_map[] = { /* RAM */ .virt = 0x40000000UL, .phys = 0x40000000UL, - .size = 0xC0000000UL, + .size = CONFIG_SUNXI_DRAM_MAX_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -65,6 +65,15 @@ static struct mm_region sunxi_mem_map[] = { } }; struct mm_region *mem_map = sunxi_mem_map; + +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Some devices (like the EMAC) have a 32-bit DMA limit. */ + if (gd->ram_top > (1ULL << 32)) + return 1ULL << 32; + + return gd->ram_top; +} #endif static int gpio_init(void) |