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| author | Rajesh Bhagat <rajesh.bhagat@nxp.com> | 2021-02-11 13:28:49 +0100 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2021-03-05 10:25:41 +0530 |
| commit | 504debcd8c1f4d86682ed8f3c7472284a2b6e822 (patch) | |
| tree | 5e58d9bd92a8435a5e96dbc400f6ca478b0c76a2 /arch | |
| parent | b5ee48c099e4036fc0336cf66a0d324b8225d53e (diff) | |
| download | u-boot-504debcd8c1f4d86682ed8f3c7472284a2b6e822.zip u-boot-504debcd8c1f4d86682ed8f3c7472284a2b6e822.tar.gz u-boot-504debcd8c1f4d86682ed8f3c7472284a2b6e822.tar.bz2 | |
configs: fsl: move bootrom specific defines to Kconfig
Moves below bootrom specific defines to Kconfig:
CONFIG_SYS_FSL_BOOTROM_BASE
CONFIG_SYS_FSL_BOOTROM_SIZE
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 10 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 |
2 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 4d46587..ae0b7b2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -640,3 +640,13 @@ config HAS_FSL_XHCI_USB help For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use pins, select it when the pins are assigned to USB. + +config SYS_FSL_BOOTROM_BASE + hex + depends on FSL_LSCH2 + default 0 + +config SYS_FSL_BOOTROM_SIZE + hex + depends on FSL_LSCH2 + default 0x1000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 4335aa0..c51b65e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -69,8 +69,6 @@ #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 #endif #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0 -#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 |