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authorXie Xiaobo <r63061@freescale.com>2011-10-03 12:18:39 -0700
committerKumar Gala <galak@kernel.crashing.org>2011-10-09 17:57:54 -0500
commitae2044d8b30bf82fef5550497a0d4315edf6b62e (patch)
tree3eabede99421d873d4a7ee5062d90c4fc8af89e1 /arch
parent867b06f434a3184deeabd2bddb5178439dc6e445 (diff)
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powerpc/mpc8536ds: Add eSPI support for MPC8536DS
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index fb5ef91..a29fe35 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1934,7 +1934,12 @@ typedef struct ccsr_gur {
u8 res1[8];
u32 gpporcr; /* General-purpose POR configuration */
u8 res2[12];
+#if defined(CONFIG_MPC8536)
+ u32 gencfgr; /* General Configuration Register */
+#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
+#else
u32 gpiocr; /* GPIO control */
+#endif
u8 res3[12];
#if defined(CONFIG_MPC8569)
u32 plppar1; /* Platform port pin assignment 1 */