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| author | Ye Li <ye.li@nxp.com> | 2021-10-29 09:46:26 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:39 +0100 |
| commit | 55a7e7882da16d0a3e15a6dedf8fdb509b6fdf74 (patch) | |
| tree | 790c73c52329d261c3ecfa74c184c9738493d33d /arch | |
| parent | 9c7fbebe5dd5d9daa9160b778432daef2a13f47f (diff) | |
| download | u-boot-55a7e7882da16d0a3e15a6dedf8fdb509b6fdf74.zip u-boot-55a7e7882da16d0a3e15a6dedf8fdb509b6fdf74.tar.gz u-boot-55a7e7882da16d0a3e15a6dedf8fdb509b6fdf74.tar.bz2 | |
imx8ulp: clock: Reset DDR controller before clock enable
The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index e599e6c..f54fc25 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -97,6 +97,9 @@ void ddrphy_pll_lock(void) void init_clk_ddr(void) { + /* disable the ddr pcc */ + writel(0xc0000000, PCC5_LPDDR4_ADDR); + /* enable pll4 and ddrclk*/ cgc2_pll4_init(); cgc2_ddrclk_config(1, 1); |