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| author | Samuel Holland <samuel@sholland.org> | 2023-10-31 00:37:20 -0500 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-02 15:15:54 +0800 |
| commit | bade208b5deb16120c6236e941c6e5f081e86c05 (patch) | |
| tree | edd244a408ee39723cd49de76291b16d8c0aeb88 /arch | |
| parent | 3b00fab616b1150da745bbb36f6644842a24624f (diff) | |
| download | u-boot-bade208b5deb16120c6236e941c6e5f081e86c05.zip u-boot-bade208b5deb16120c6236e941c6e5f081e86c05.tar.gz u-boot-bade208b5deb16120c6236e941c6e5f081e86c05.tar.bz2 | |
riscv: Weakly define invalidate_icache_range()
Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
vendor-specific way to invalidate a portion of the instruction cache.
Allow them to override invalidate_icache_range().
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/lib/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index c46b49e..afad7e1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -19,7 +19,7 @@ __weak void flush_dcache_range(unsigned long start, unsigned long end) { } -void invalidate_icache_range(unsigned long start, unsigned long end) +__weak void invalidate_icache_range(unsigned long start, unsigned long end) { /* * RISC-V does not have an instruction for invalidating parts of the |