diff options
| author | Michal Simek <michal.simek@amd.com> | 2023-11-01 13:06:15 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-11-07 13:47:09 +0100 |
| commit | 6504242df367bf1934fb6c8f0714f038e127a7e1 (patch) | |
| tree | 4d0675cf9708181ab3af2d0196b55908c0bf3df7 /arch | |
| parent | 1332a781e1ae214ee01af49454c1622cc9433517 (diff) | |
| download | u-boot-6504242df367bf1934fb6c8f0714f038e127a7e1.zip u-boot-6504242df367bf1934fb6c8f0714f038e127a7e1.tar.gz u-boot-6504242df367bf1934fb6c8f0714f038e127a7e1.tar.bz2 | |
arm64: zynqmp: Add description for nvmem efuse layout
Based on discussion with DT folks at link below there is not going to be
any name restrictions for child names. That's why add description for
current nvmem layout.
Link: https://lore.kernel.org/lkml/20231013101450.573-3-praveen.teja.kundanala@amd.com/
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/af81299cafc2bd13ed30dcd69bdf6efb5fbb7f68.1698840373.git.michal.simek@amd.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 66d5335..58a56bc 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -214,6 +214,55 @@ soc_revision: soc-revision@0 { reg = <0x0 0x4>; }; + /* efuse access */ + efuse_dna: efuse-dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse-usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse-usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse-usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse-usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse-usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse-usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse-usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse-usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse-miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse-chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse-pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse-sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse-spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_ppk0hash: efuse-ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse-ppk1hash@d0 { + reg = <0xd0 0x30>; + }; }; zynqmp_pcap: pcap { |