arm: Remove strongarm support

There are no platforms using this architecture anymore, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>

8 files changed, 1 insertions, 389 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 434c5e9..163e94f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -330,11 +330,6 @@ config CPU_V7R
 	select SYS_ARM_MPU
 	select SYS_CACHE_SHIFT_6
 
-config CPU_SA1100
-	bool
-	select SYS_CACHE_SHIFT_5
-	imply SYS_ARM_MMU
-
 config SYS_CPU
 	default "arm720t" if CPU_ARM720T
 	default "arm920t" if CPU_ARM920T
@@ -345,7 +340,6 @@ config SYS_CPU
 	default "armv7" if CPU_V7A
 	default "armv7" if CPU_V7R
 	default "armv7m" if CPU_V7M
-	default "sa1100" if CPU_SA1100
 	default "armv8" if ARM64
 
 config SYS_ARM_ARCH
@@ -359,7 +353,6 @@ config SYS_ARM_ARCH
 	default 7 if CPU_V7A
 	default 7 if CPU_V7M
 	default 7 if CPU_V7R
-	default 4 if CPU_SA1100
 	default 8 if ARM64
 
 choice
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 09fc318..a376030 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -10,7 +10,6 @@ arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
 arch-$(CONFIG_CPU_ARM920T)	=-march=armv4t
 arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
 arch-$(CONFIG_CPU_ARM946ES)	=-march=armv5te
-arch-$(CONFIG_CPU_SA1100)	=-march=armv4
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5t
 arch-$(CONFIG_CPU_ARM1176)	=-march=armv5t
 arch-$(CONFIG_CPU_V7A)		=$(call cc-option, -march=armv7-a, \
@@ -39,7 +38,6 @@ tune-$(CONFIG_CPU_ARM720T)	=-mtune=arm7tdmi
 tune-$(CONFIG_CPU_ARM920T)	=
 tune-$(CONFIG_CPU_ARM926EJS)	=
 tune-$(CONFIG_CPU_ARM946ES)	=
-tune-$(CONFIG_CPU_SA1100)	=-mtune=strongarm1100
 tune-$(CONFIG_CPU_ARM1136)	=
 tune-$(CONFIG_CPU_ARM1176)	=
 tune-$(CONFIG_CPU_V7A)		=-mtune=generic-armv7-a
diff --git a/arch/arm/cpu/sa1100/Makefile b/arch/arm/cpu/sa1100/Makefile
deleted file mode 100644
index 3819309..0000000
--- a/arch/arm/cpu/sa1100/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-extra-y	= start.o
-
-obj-y	+= cpu.o
-obj-y	+= timer.o
diff --git a/arch/arm/cpu/sa1100/cpu.c b/arch/arm/cpu/sa1100/cpu.c
deleted file mode 100644
index 6f67f7f..0000000
--- a/arch/arm/cpu/sa1100/cpu.c
+++ /dev/null
@@ -1,65 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <irq_func.h>
-#include <asm/system.h>
-#include <asm/io.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * just disable everything that can disturb booting linux
-	 */
-
-	disable_interrupts();
-
-	/* turn off I-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I-cache */
-	cache_flush();
-
-	return (0);
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-}
-
-#define RST_BASE 0x90030000
-#define RSRR	0x00
-#define RCSR	0x04
-
-__attribute__((noreturn)) void reset_cpu(void)
-{
-	/* repeat endlessly */
-	while (1) {
-		writel(0, RST_BASE + RCSR);
-		writel(1, RST_BASE + RSRR);
-	}
-}
diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S
deleted file mode 100644
index 2f84f20..0000000
--- a/arch/arm/cpu/sa1100/start.S
+++ /dev/null
@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  armboot - Startup Code for SA1100 CPU
- *
- *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
- *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- *  Copyright (C) 2000	Wolfgang Denk <wd@denx.de>
- *  Copyright (c) 2001	Alex Züpke <azu@sysgo.de>
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-	.globl	reset
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
-	bl	cpu_init_crit
-#endif
-
-	bl	_main
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
-	mov	pc, lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-/* Interrupt-Controller base address */
-IC_BASE:	.word	0x90050000
-#define ICMR	0x04
-
-
-/* Reset-Controller */
-RST_BASE:		.word   0x90030000
-#define RSRR	0x00
-#define RCSR	0x04
-
-
-/* PWR */
-PWR_BASE:		.word   0x90020000
-#define PSPR    0x08
-#define PPCR    0x14
-cpuspeed:		.word   CONFIG_SYS_CPUSPEED
-
-
-cpu_init_crit:
-	/*
-	 * mask all IRQs
-	 */
-	ldr	r0, IC_BASE
-	mov	r1, #0x00
-	str	r1, [r0, #ICMR]
-
-	/* set clock speed */
-	ldr	r0, PWR_BASE
-	ldr	r1, cpuspeed
-	str	r1, [r0, #PPCR]
-
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip,	lr
-	bl	lowlevel_init
-	mov	lr,	ip
-#endif
-
-	/*
-	 * disable MMU stuff and enable I-cache
-	 */
-	mrc	p15,0,r0,c1,c0
-	bic	r0, r0, #0x00002000	@ clear bit 13 (X)
-	bic	r0, r0, #0x0000000f	@ clear bits 3-0 (WCAM)
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) Icache
-	orr	r0, r0, #0x00000002	@ set bit 1 (A) Align
-	mcr	p15,0,r0,c1,c0
-
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	mov	pc, lr
diff --git a/arch/arm/cpu/sa1100/timer.c b/arch/arm/cpu/sa1100/timer.c
deleted file mode 100644
index a5cdaf5..0000000
--- a/arch/arm/cpu/sa1100/timer.c
+++ /dev/null
@@ -1,66 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- */
-
-#include <common.h>
-#include <SA-1100.h>
-#include <time.h>
-#include <linux/delay.h>
-
-static ulong get_timer_masked (void)
-{
-	return OSCR;
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked ();
-}
-
-void __udelay(unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/include/asm/arch-sa1100/bitfield.h b/arch/arm/include/asm/arch-sa1100/bitfield.h
deleted file mode 100644
index 104a21c..0000000
--- a/arch/arm/include/asm/arch-sa1100/bitfield.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *	FILE		bitfield.h
- *
- *	Version		1.1
- *	Author		Copyright (c) Marc A. Viredaz, 1998
- *			DEC Western Research Laboratory, Palo Alto, CA
- *	Date		April 1998 (April 1997)
- *	System		Advanced RISC Machine (ARM)
- *	Language	C or ARM Assembly
- *	Purpose		Definition of macros to operate on bit fields.
- */
-
-
-#ifndef __BITFIELD_H
-#define __BITFIELD_H
-
-#ifndef __ASSEMBLY__
-#define UData(Data)	((unsigned long) (Data))
-#else
-#define UData(Data)	(Data)
-#endif
-
-
-/*
- * MACRO: Fld
- *
- * Purpose
- *    The macro "Fld" encodes a bit field, given its size and its shift value
- *    with respect to bit 0.
- *
- * Note
- *    A more intuitive way to encode bit fields would have been to use their
- *    mask. However, extracting size and shift value information from a bit
- *    field's mask is cumbersome and might break the assembler (255-character
- *    line-size limit).
- *
- * Input
- *    Size		Size of the bit field, in number of bits.
- *    Shft		Shift value of the bit field with respect to bit 0.
- *
- * Output
- *    Fld		Encoded bit field.
- */
-
-#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
-
-
-/*
- * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
- *
- * Purpose
- *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
- *    the size, shift value, mask, aligned mask, and first bit of a
- *    bit field.
- *
- * Input
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FSize		Size of the bit field, in number of bits.
- *    FShft		Shift value of the bit field with respect to bit 0.
- *    FMsk		Mask for the bit field.
- *    FAlnMsk		Mask for the bit field, aligned on bit 0.
- *    F1stBit		First bit of the bit field.
- */
-
-#define FSize(Field)	((Field) >> 16)
-#define FShft(Field)	((Field) & 0x0000FFFF)
-#define FMsk(Field)	(((UData (1) << FSize (Field)) - 1) << FShft (Field))
-#define FAlnMsk(Field)	((UData (1) << FSize (Field)) - 1)
-#define F1stBit(Field)	(UData (1) << FShft (Field))
-
-
-/*
- * MACRO: FInsrt
- *
- * Purpose
- *    The macro "FInsrt" inserts a value into a bit field by shifting the
- *    former appropriately.
- *
- * Input
- *    Value		Bit-field value.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FInsrt		Bit-field value positioned appropriately.
- */
-
-#define FInsrt(Value, Field) \
-			(UData (Value) << FShft (Field))
-
-
-/*
- * MACRO: FExtr
- *
- * Purpose
- *    The macro "FExtr" extracts the value of a bit field by masking and
- *    shifting it appropriately.
- *
- * Input
- *    Data		Data containing the bit-field to be extracted.
- *    Field		Encoded bit field (using the macro "Fld").
- *
- * Output
- *    FExtr		Bit-field value.
- */
-
-#define FExtr(Data, Field) \
-			((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
-
-
-#endif /* __BITFIELD_H */
diff --git a/arch/arm/include/asm/proc-armv/system.h b/arch/arm/include/asm/proc-armv/system.h
index c61374e..a1f59d9 100644
--- a/arch/arm/include/asm/proc-armv/system.h
+++ b/arch/arm/include/asm/proc-armv/system.h
@@ -163,8 +163,7 @@
 
 #endif	/* CONFIG_ARM64 */
 
-#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) || \
-	defined(CONFIG_ARM64)
+#if defined(CONFIG_ARM64)
 /*
  * On the StrongARM, "swp" is terminally broken since it bypasses the
  * cache totally.  This means that the cache becomes inconsistent, and,