Merge branch '2022-11-02-assorted-updates'

- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
  driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
  bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
  updates.

14 files changed, 70 insertions, 30 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 710f171..453bef9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -769,6 +769,8 @@ config ARCH_HIGHBANK
 	select AHCI
 	select DM_ETH
 	select PHYS_64BIT
+	select TIMER
+	select SP804_TIMER
 	imply OF_HAS_PRIOR_STAGE
 
 config ARCH_INTEGRATOR
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 02c3fdf..57b0f53 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -859,4 +859,22 @@
 		clock-names = "fck";
 		max-functions = /bits/ 8 <1>;
 	};
+
+	main_rti0: watchdog@e000000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0xe000000 0x00 0x100>;
+		clocks = <&k3_clks 125 0>;
+		power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 125 0>;
+		assigned-clock-parents = <&k3_clks 125 2>;
+	};
+
+	main_rti1: watchdog@e010000 {
+		compatible = "ti,j7-rti-wdt";
+		reg = <0x00 0xe010000 0x00 0x100>;
+		clocks = <&k3_clks 126 0>;
+		power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 126 0>;
+		assigned-clock-parents = <&k3_clks 126 2>;
+	};
 };
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
index 7aa94d5..053e7f4 100644
--- a/arch/arm/dts/k3-am64.dtsi
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -70,6 +70,8 @@
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
 			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
 			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
+			 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
 			 <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
 			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
 			 <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c
index 01d652a..939c0f7 100644
--- a/arch/arm/lib/semihosting.c
+++ b/arch/arm/lib/semihosting.c
@@ -4,11 +4,6 @@
  * Copyright 2014 Broadcom Corporation
  */
 
-/*
- * This code has been tested on arm64/aarch64 fastmodel only.  An untested
- * placeholder exists for armv7 architectures, but since they are commonly
- * available in silicon now, fastmodel usage makes less sense for them.
- */
 #include <common.h>
 #include <log.h>
 #include <semihosting.h>
@@ -26,19 +21,42 @@
 #define SYSERRNO	0x13
 
 /*
- * Call the handler
+ * Macro to force the compiler to *populate* memory (for an array or struct)
+ * before passing the pointer to an inline assembly call.
  */
-static noinline long smh_trap(unsigned int sysnum, void *addr)
-{
-	register long result asm("r0");
+#define USE_PTR(ptr) *(const char (*)[]) (ptr)
+
 #if defined(CONFIG_ARM64)
-	asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
+	#define SMH_TRAP "hlt #0xf000"
 #elif defined(CONFIG_CPU_V7M)
-	asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
+	#define SMH_TRAP "bkpt #0xAB"
+#elif defined(CONFIG_SYS_THUMB_BUILD)
+	#define SMH_TRAP "svc #0xab"
 #else
-	/* Note - untested placeholder */
-	asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr) : "memory");
+	#define SMH_TRAP "svc #0x123456"
 #endif
+
+/*
+ * Call the handler
+ */
+static long smh_trap(unsigned int sysnum, void *addr)
+{
+	register long result asm("r0");
+	register void *_addr asm("r1") = addr;
+
+	/*
+	 * We need a memory clobber (aka compiler barrier) for two reasons:
+	 * - The compiler needs to populate any data structures pointed to
+	 *   by "addr" *before* the trap instruction is called.
+	 * - At least the SYSREAD function puts the result into memory pointed
+	 *   to by "addr", so the compiler must not use a cached version of
+	 *   the previous content, after the call has finished.
+	 */
+	asm volatile (SMH_TRAP
+		      : "=r" (result)
+		      : "0"(sysnum), "r"(USE_PTR(_addr))
+		      : "memory");
+
 	return result;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 92a7e60..90f024d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -446,7 +446,7 @@ ulong cpu_init_f(void)
 /* Implement a dummy function for those platforms w/o SERDES */
 static void __fsl_serdes__init(void)
 {
-	return ;
+	return;
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 8d629d3..e6d3058 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -76,7 +76,7 @@ void setup_ifc(void)
 	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
 	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
 
-	return ;
+	return;
 }
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index c8ad6a1..61d8aa7 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -271,13 +271,13 @@ static inline void ft_fixup_l2cache(void *blob)
 
 	if (ph == NULL) {
 		debug("no next-level-cache property\n");
-		return ;
+		return;
 	}
 
 	off = fdt_node_offset_by_phandle(blob, *ph);
 	if (off < 0) {
 		printf("%s: %s\n", __func__, fdt_strerror(off));
-		return ;
+		return;
 	}
 
 	ft_fixup_l2cache_compatible(blob, off);
@@ -373,7 +373,7 @@ next:
 		l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 		if (l3_off < 0) {
 			printf("%s: %s\n", __func__, fdt_strerror(off));
-			return ;
+			return;
 		}
 		ft_fixup_l3cache(blob, l3_off);
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index a084002..34974c9 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -111,7 +111,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
 #endif
 	default:
 		printf("Error: Invalid device type to %s\n", __FUNCTION__);
-		return ;
+		return;
 	}
 
 	base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0];
@@ -232,7 +232,7 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 	/* search for srio node, if doesn't exist just return - nothing todo */
 	srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio");
 	if (srio_off < 0)
-		return ;
+		return;
 
 	for (i = 0; i < srio_liodn_tbl_sz; i++) {
 		int off, portid = tbl[i].portid;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 2a5c3e3..38f30af 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -45,7 +45,7 @@ void fsl_serdes_init(void)
 
 	if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
 		printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
-		return ;
+		return;
 	}
 
 	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 52e2124..6b4cbdd 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -21,7 +21,7 @@ void fdt_portal(void *blob, const char *compat, const char *container,
 
 	off = fdt_node_offset_by_compatible(blob, -1, compat);
 	if (off < 0)
-		return ;
+		return;
 
 	off = fdt_parent_offset(blob, off);
 	/* if non-zero assume we have a container */
@@ -35,7 +35,7 @@ void fdt_portal(void *blob, const char *compat, const char *container,
 		range = fdt_getprop_w(blob, off, "ranges", &len);
 		if (range == NULL) {
 			printf("ERROR: container for %s has no ranges", compat);
-			return ;
+			return;
 		}
 
 		range[0] = 0;
@@ -61,13 +61,13 @@ void fdt_portal(void *blob, const char *compat, const char *container,
 		if (container && (memcmp(container, name, len))) {
 			printf("WARNING: container names didn't match %s %s\n",
 				container, name);
-			return ;
+			return;
 		}
 
 		memcpy(&buf, name, len);
 		len += sprintf(&buf[len], "@%llx", addr);
 		fdt_set_name(blob, off, buf);
-		return ;
+		return;
 	}
 
 	printf("ERROR: %s isn't in a container.  Not supported\n", compat);
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index e39fe14..81e6072 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -41,7 +41,7 @@ __weak void init_tlbs(void)
 			  tlb_table[i].mas7);
 	}
 
-	return ;
+	return;
 }
 
 #if !defined(CONFIG_NAND_SPL) && \
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 871554a..3004290 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -128,7 +128,7 @@ void ft_srio_setup(void *blob)
 	/* search for srio node, if doesn't exist just return - nothing todo */
 	srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio");
 	if (srio_off < 0)
-		return ;
+		return;
 
 #ifdef CONFIG_SRIO1
 	if (is_serdes_configured(SRIO1))
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 198b5b1..24bbe3b 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -353,5 +353,5 @@ void init_laws(void)
 	}
 #endif
 
-	return ;
+	return;
 }
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 5127878..8ae8d8a 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -113,7 +113,7 @@ static void boot_jump_linux(struct bootm_headers *images)
 			   cmd_start, cmd_end, 0, 0);
 		/* does not return */
 	}
-	return ;
+	return;
 }
 
 void arch_lmb_reserve(struct lmb *lmb)
@@ -148,7 +148,7 @@ void arch_lmb_reserve(struct lmb *lmb)
 	cpu_mp_lmb_reserve(lmb);
 #endif
 
-	return ;
+	return;
 }
 
 static void boot_prep_linux(struct bootm_headers *images)