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| author | Rick Chen <rick@andestech.com> | 2017-12-26 13:55:50 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-12 08:05:12 -0500 |
| commit | 039ed7c57245b139986bc78e9f951e55c2039c47 (patch) | |
| tree | b99c1fb013426b2a6028d29e77d9ebcc09fea7f5 /arch | |
| parent | 8bbb2909cbce083f35317d6a7279d02a82f21892 (diff) | |
| download | u-boot-039ed7c57245b139986bc78e9f951e55c2039c47.zip u-boot-039ed7c57245b139986bc78e9f951e55c2039c47.tar.gz u-boot-039ed7c57245b139986bc78e9f951e55c2039c47.tar.bz2 | |
riscv: nx25: dts: Add AE250 dts to support RISC-V
AE250 is the Soc using NX25 cpu core base on RISC-V arch.
Details please see the doc/README.ae250.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/dts/Makefile | 14 | ||||
| -rw-r--r-- | arch/riscv/dts/ae250.dts | 96 |
2 files changed, 110 insertions, 0 deletions
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile new file mode 100644 index 0000000..718b99f --- /dev/null +++ b/arch/riscv/dts/Makefile @@ -0,0 +1,14 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_TARGET_NX25_AE250) += ae250.dtb +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/riscv/dts/ae250.dts b/arch/riscv/dts/ae250.dts new file mode 100644 index 0000000..5dc4fb0 --- /dev/null +++ b/arch/riscv/dts/ae250.dts @@ -0,0 +1,96 @@ +/dts-v1/; +/ { + compatible = "riscv32 nx25"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + ethernet0 = &mac0; + spi0 = &spi; + } ; + + chosen { + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + spiclk: virt_100mhz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <19660800>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <40000000>; + }; + + mac0: mac@e0100000 { + compatible = "andestech,atmac100"; + reg = <0xe0100000 0x1000>; + interrupts = <25 4>; + }; + + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + max-frequency = <100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + + spi: spi@f0b00000 { + compatible = "andestech,atcspi200"; + reg = <0xf0b00000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + clocks = <&spiclk>; + interrupts = <3 4>; + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-cpol; + spi-cpha; + }; + }; + +}; |