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| author | Simon Glass <sjg@chromium.org> | 2019-09-25 08:11:47 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2019-10-08 13:57:37 +0800 |
| commit | bdeb2bccbf40474eca8ef039ab794ba46cd971e5 (patch) | |
| tree | 8c58d5fd9d6f1c3347698a57b8e31b7073ab8b04 /arch | |
| parent | ebe002cd180c4b9f7f92720acaf13e712a1cce93 (diff) | |
| download | u-boot-bdeb2bccbf40474eca8ef039ab794ba46cd971e5.zip u-boot-bdeb2bccbf40474eca8ef039ab794ba46cd971e5.tar.gz u-boot-bdeb2bccbf40474eca8ef039ab794ba46cd971e5.tar.bz2 | |
x86: Rename turbo ratio MSR to MSR_TURBO_RATIO_LIMIT
This MSR number is used on most modern Intel processors, so drop the
confusing NHM prefix (which might mean Nehalem).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: drop MSR_IVT_TURBO_RATIO_LIMIT as no code uses it]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/cpu/broadwell/cpu_full.c | 2 | ||||
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 3 |
2 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/cpu/broadwell/cpu_full.c b/arch/x86/cpu/broadwell/cpu_full.c index bd0b203..9686cf5 100644 --- a/arch/x86/cpu/broadwell/cpu_full.c +++ b/arch/x86/cpu/broadwell/cpu_full.c @@ -346,7 +346,7 @@ static void set_max_ratio(void) /* Check for configurable TDP option */ if (turbo_get_state() == TURBO_ENABLED) { - msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT); + msr = msr_read(MSR_TURBO_RATIO_LIMIT); perf_ctl.lo = (msr.lo & 0xff) << 8; } else if (cpu_config_tdp_levels()) { /* Set to nominal TDP ratio */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1a02d8c..6cb5870 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -101,8 +101,7 @@ #define MSR_OFFCORE_RSP_1 0x000001a7 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad -#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae +#define MSR_TURBO_RATIO_LIMIT 0x000001ad #define MSR_IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 |