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authorElaine Zhang <zhangqing@rock-chips.com>2021-10-12 16:43:00 +0800
committerKever Yang <kever.yang@rock-chips.com>2021-10-15 20:57:31 +0800
commitf2cdd44adb9f06f455185b4882cfd91e8d75d58a (patch)
tree089bd253b6b62f1c75c355d0f2bfdc0e56e1e48c /arch
parent24c627b57a090b141a3088208e3f70b6f28dc3d8 (diff)
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clk: rockchip: rk3568: update clks
fix up ppll init freq. support tclk_emmc. add freq (26M) for mmc device. fix up the sfc clk rate unit error. Change in V2: remove change id. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-rockchip/cru_rk3568.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
index 6c59033..399f19a 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -14,7 +14,7 @@
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
-#define PPLL_HZ (100 * MHz)
+#define PPLL_HZ (200 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {