Merge tag 'fsl-qoriq-for-v2019.04-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for more boards

Add TFA boot defconfig for ls1088a and ls2088a.
Add dts fixup for PCIe endpoint and root complex.

11 files changed, 53 insertions, 28 deletions

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 2b086da..01c5068 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -89,7 +89,7 @@ config ARCH_LS1046A
 config ARCH_LS1088A
 	bool
 	select ARMV8_SET_SMPEN
-	select ARM_ERRATA_855873
+	select ARM_ERRATA_855873 if !TFABOOT
 	select FSL_LSCH3
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
@@ -98,11 +98,11 @@ config ARCH_LS1088A
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_EC1
 	select SYS_FSL_EC2
-	select SYS_FSL_ERRATUM_A009803
-	select SYS_FSL_ERRATUM_A009942
-	select SYS_FSL_ERRATUM_A010165
-	select SYS_FSL_ERRATUM_A008511
-	select SYS_FSL_ERRATUM_A008850
+	select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+	select SYS_FSL_ERRATUM_A010165 if !TFABOOT
+	select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+	select SYS_FSL_ERRATUM_A008850 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_DDR4
@@ -145,20 +145,20 @@ config ARCH_LS2080A
 	select SYS_FSL_SRDS_2
 	select FSL_TZASC_1
 	select FSL_TZASC_2
-	select SYS_FSL_ERRATUM_A008336
-	select SYS_FSL_ERRATUM_A008511
-	select SYS_FSL_ERRATUM_A008514
+	select SYS_FSL_ERRATUM_A008336 if !TFABOOT
+	select SYS_FSL_ERRATUM_A008511 if !TFABOOT
+	select SYS_FSL_ERRATUM_A008514 if !TFABOOT
 	select SYS_FSL_ERRATUM_A008585
 	select SYS_FSL_ERRATUM_A008997
 	select SYS_FSL_ERRATUM_A009007
 	select SYS_FSL_ERRATUM_A009008
 	select SYS_FSL_ERRATUM_A009635
-	select SYS_FSL_ERRATUM_A009663
+	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009798
 	select SYS_FSL_ERRATUM_A009801
-	select SYS_FSL_ERRATUM_A009803
-	select SYS_FSL_ERRATUM_A009942
-	select SYS_FSL_ERRATUM_A010165
+	select SYS_FSL_ERRATUM_A009803 if !TFABOOT
+	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
+	select SYS_FSL_ERRATUM_A010165 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009203
 	select ARCH_EARLY_INIT_R
 	select BOARD_EARLY_INIT_F
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 1fc025b..be21685 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -51,7 +51,9 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
 	CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
 	CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+	CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
 	CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+	CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
 	CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
@@ -675,7 +677,7 @@ enum boot_src __get_boot_src(u32 porsr1)
 			break;
 		case RCW_SRC_EMMC_VAL:
 		/* RCW SRC EMMC */
-			src = BOOT_SOURCE_SD_MMC2;
+			src = BOOT_SOURCE_SD_MMC;
 			break;
 		case RCW_SRC_I2C1_VAL:
 		/* RCW SRC I2C1 Extended */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index c9c2c3f..1111765 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -327,7 +327,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
 	memcpy((char *)tmp, p, len);
 
 	val = fdt32_to_cpu(tmp[0][6]);
-	if (rev > REV1_0) {
+	if (rev == REV1_0) {
 		tmp[1][6] = cpu_to_fdt32(val + 1);
 		tmp[2][6] = cpu_to_fdt32(val + 2);
 		tmp[3][6] = cpu_to_fdt32(val + 3);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0092a22..06f3edb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -684,7 +684,7 @@ int qspi_ahb_init(void)
 #endif
 
 #ifdef CONFIG_TFABOOT
-#define MAX_BOOTCMD_SIZE	256
+#define MAX_BOOTCMD_SIZE	512
 
 int fsl_setenv_bootcmd(void)
 {
@@ -812,6 +812,17 @@ int board_late_init(void)
 		fsl_setenv_bootcmd();
 		fsl_setenv_mcinitcmd();
 	}
+
+	/*
+	 * If the boot mode is secure, default environment is not present then
+	 * setenv command needs to be run by default
+	 */
+#ifdef CONFIG_CHAIN_OF_TRUST
+	if ((fsl_check_boot_mode_secure() == 1)) {
+		fsl_setenv_bootcmd();
+		fsl_setenv_mcinitcmd();
+	}
+#endif
 #endif
 #ifdef CONFIG_QSPI_AHB_INIT
 	qspi_ahb_init();
diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
index c8bf9a0..b6d4f0f 100644
--- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
+++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
@@ -56,3 +56,7 @@
 		reg = <1>;
 	};
 };
+
+&sata {
+	status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a-iot.dtsi b/arch/arm/dts/ls1021a-iot.dtsi
index 3371b9f..d27b601 100644
--- a/arch/arm/dts/ls1021a-iot.dtsi
+++ b/arch/arm/dts/ls1021a-iot.dtsi
@@ -12,9 +12,9 @@
 	model = "LS1021A IOT Board";
 
 	aliases {
-		enet2_rgmii_phy = &rgmii_phy1;
-		enet0_sgmii_phy = &sgmii_phy2;
-		enet1_sgmii_phy = &sgmii_phy0;
+		enet2-rgmii-phy = &rgmii_phy1;
+		enet0-sgmii-phy = &sgmii_phy2;
+		enet1-sgmii-phy = &sgmii_phy0;
 		spi0 = &qspi;
 		spi1 = &dspi1;
 	};
diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi
index 47c128f..f7783e5 100644
--- a/arch/arm/dts/ls1021a-qds.dtsi
+++ b/arch/arm/dts/ls1021a-qds.dtsi
@@ -11,11 +11,11 @@
 	model = "LS1021A QDS Board";
 
 	aliases {
-		enet0_rgmii_phy = &rgmii_phy1;
-		enet1_rgmii_phy = &rgmii_phy2;
-		enet2_rgmii_phy = &rgmii_phy3;
-		enet0_sgmii_phy = &sgmii_phy1c;
-		enet1_sgmii_phy = &sgmii_phy1d;
+		enet0-rgmii-phy = &rgmii_phy1;
+		enet1-rgmii-phy = &rgmii_phy2;
+		enet2-rgmii-phy = &rgmii_phy3;
+		enet0-sgmii-phy = &sgmii_phy1c;
+		enet1-sgmii-phy = &sgmii_phy1d;
 		spi0 = &qspi;
 		spi1 = &dspi0;
 	};
diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi
index 14e0cea..928e100 100644
--- a/arch/arm/dts/ls1021a-twr.dtsi
+++ b/arch/arm/dts/ls1021a-twr.dtsi
@@ -11,9 +11,9 @@
 	model = "LS1021A TWR Board";
 
 	aliases {
-		enet2_rgmii_phy = &rgmii_phy1;
-		enet0_sgmii_phy = &sgmii_phy2;
-		enet1_sgmii_phy = &sgmii_phy0;
+		enet2-rgmii-phy = &rgmii_phy1;
+		enet0-sgmii-phy = &sgmii_phy2;
+		enet1-sgmii-phy = &sgmii_phy0;
 		spi0 = &qspi;
 		spi1 = &dspi1;
 	};
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index a3f473f..f375fe7 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -55,7 +55,11 @@ void fdt_fixup_icid(void *blob);
 		CONFIG_SYS_FSL_ESDHC_ADDR)
 
 #define SET_QDMA_ICID(compat, streamid) \
-	SET_SCFG_ICID(compat, streamid, dma_icid,\
+	SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \
+		QDMA_BASE_ADDR), \
+	SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \
+		QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \
 		QDMA_BASE_ADDR)
 
 #define SET_EDMA_ICID(streamid) \
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 4d0f16f..b4b7c34 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -94,6 +94,7 @@
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 
 #define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+#define QMAN_CQSIDR_REG				0x20a80
 
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index f5bef6d..7d95c4e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -80,6 +80,9 @@ enum boot_src get_boot_src(void);
 #define SVR_LS1012A		0x870400
 #define SVR_LS1043A		0x879200
 #define SVR_LS1023A		0x879208
+/* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER */
+#define SVR_LS1043A_P23		0x879202
+#define SVR_LS1023A_P23		0x87920A
 #define SVR_LS1046A		0x870700
 #define SVR_LS1026A		0x870708
 #define SVR_LS1048A		0x870320