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authorSimon Glass <sjg@chromium.org>2020-12-19 10:39:57 -0700
committerSimon Glass <sjg@chromium.org>2021-01-05 12:24:41 -0700
commit366c4eb4b5df420de3cc32be3089bef68a883d97 (patch)
treeddfd15ef97a49ef8325211c494e2fd3785a5bd9a /arch/x86/include
parent370746ada7cfd93de248c2274618ba635f9d1f46 (diff)
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x86: apl: Move priv/plat structs to headers
With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/arch-apollolake/gpio.h18
-rw-r--r--arch/x86/include/asm/arch-apollolake/hostbridge.h28
-rw-r--r--arch/x86/include/asm/arch-apollolake/pmc.h16
3 files changed, 62 insertions, 0 deletions
diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h
index ab5860c..762160d 100644
--- a/arch/x86/include/asm/arch-apollolake/gpio.h
+++ b/arch/x86/include/asm/arch-apollolake/gpio.h
@@ -485,4 +485,22 @@
/* This is needed by ACPI */
#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */
+#ifndef __ASSEMBLY__
+
+#include <dt-structs.h>
+
+/**
+ * struct apl_gpio_plat - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ /* Put this first since driver model will copy the data here */
+ struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+#endif /* __ASSEMBLY__ */
+
#endif /* _ASM_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/hostbridge.h b/arch/x86/include/asm/arch-apollolake/hostbridge.h
new file mode 100644
index 0000000..f4dce0d
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/hostbridge.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef _ASM_ARCH_HOSTBRIDGE_H_
+#define _ASM_ARCH_HOSTBRIDGE_H_
+
+/**
+ * struct apl_hostbridge_plat - platform data for hostbridge
+ *
+ * @dtplat: Platform data for of-platdata
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_hostbridge dtplat;
+#endif
+ u32 *early_pads;
+ int early_pads_count;
+ uint pciex_region_size;
+ pci_dev_t bdf;
+};
+
+#endif /* _ASM_ARCH_HOSTBRIDGE_H_ */
diff --git a/arch/x86/include/asm/arch-apollolake/pmc.h b/arch/x86/include/asm/arch-apollolake/pmc.h
new file mode 100644
index 0000000..23ac8fe
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/pmc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#ifndef ASM_ARCH_PMC_H
+#define ASM_ARCH_PMC_H
+
+struct apl_pmc_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+ struct dtd_intel_apl_pmc dtplat;
+#endif
+ pci_dev_t bdf;
+};
+
+#endif /* ASM_ARCH_PMC_H */