diff options
| author | Simon Glass <sjg@chromium.org> | 2020-07-09 18:43:17 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-07-17 14:32:24 +0800 |
| commit | 0990c894cc2e8e94a2b049e4c83d484d0b3afd9c (patch) | |
| tree | e797cbeef5ba4fb68a87501773d48a8fba228351 /arch/x86/dts | |
| parent | ef5f5f6ca691ac0b08dfae45f8723668a9fc46b6 (diff) | |
| download | u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.zip u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.tar.gz u-boot-0990c894cc2e8e94a2b049e4c83d484d0b3afd9c.tar.bz2 | |
x86: fsp: Support a warning message when DRAM init is slow
With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.
This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.
Also add one more debug message while starting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965d9f3..a17a9c2 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -117,6 +117,7 @@ reg = <0x00000000 0 0 0 0>; compatible = "intel,apl-hostbridge"; pciex-region-size = <0x10000000>; + fspm,training-delay = <21>; /* * Parameters used by the FSP-S binary blob. This is * really unfortunate since these parameters mostly |