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author | Simon Glass <sjg@chromium.org> | 2020-12-23 08:11:28 -0700 |
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committer | Simon Glass <sjg@chromium.org> | 2021-01-05 12:24:41 -0700 |
commit | 1d2b8585f6c58f786f52dbd770b346a8386b0d41 (patch) | |
tree | b53a2cd329c533d606d5d75ba8ce293e683a71e0 /arch/x86/dts | |
parent | 7dc82591d68e2ae922abb3e78e59f2d1a6d13c4e (diff) | |
download | u-boot-1d2b8585f6c58f786f52dbd770b346a8386b0d41.zip u-boot-1d2b8585f6c58f786f52dbd770b346a8386b0d41.tar.gz u-boot-1d2b8585f6c58f786f52dbd770b346a8386b0d41.tar.bz2 |
x86: coral: Move fsp-m settings to a subnode
At present these settings are in the node for host-bridge and so are
visible in TPL as well as SPL. But they are only used for SPL.
Move them to a subnode so that TPL does not included them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts')
-rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index d66e128..3c8fdf2 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -174,6 +174,9 @@ */ fsp_s: fsp-s { }; + fsp_m: fsp-m { + u-boot,dm-spl; + }; nhlt { intel,dmic-channels = <4>; @@ -650,7 +653,9 @@ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; +}; +&fsp_m { fspm,package = <PACKAGE_BGA>; fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; fspm,memory-down = <MEMORY_DOWN_YES>; |