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| author | Bin Meng <bmeng.cn@gmail.com> | 2021-07-28 12:00:23 +0800 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2021-08-02 15:11:40 +0800 |
| commit | c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68 (patch) | |
| tree | 3a15b63c5a64bbc754b58eb7be0b9d2ebc842023 /arch/x86/dts/crownbay.dts | |
| parent | 5824bc6d6fe5f63aa1fb9acbe5ad5aa28d77380f (diff) | |
| download | u-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.zip u-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.tar.gz u-boot-c79cbb5952068d9f05e4bcc7bdbbc8957fe35c68.tar.bz2 | |
x86: dts: Define a default TSC timer frequency
If for some reason, TSC timer frequency cannot be determined from
hardware, nor is it specified in the device tree, U-Boot will panic
resulting in endless reset during boot.
Let's define a default TSC timer frequency using the Kconfig value
CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of
/include/ otherwise the macro is not pre-processed).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts/crownbay.dts')
| -rw-r--r-- | arch/x86/dts/crownbay.dts | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index a7166a9..5768352 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -13,8 +13,8 @@ /include/ "pcspkr.dtsi" /include/ "reset.dtsi" /include/ "rtc.dtsi" -/include/ "tsc_timer.dtsi" +#include "tsc_timer.dtsi" #include "smbios.dtsi" / { |